Jinhai Xiao
Orcid: 0009-0009-5560-8041
According to our database1,
Jinhai Xiao authored at least 7 papers
between 2020 and 2026.
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Bibliography
2026
A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS.
IEEE J. Solid State Circuits, May, 2026
A 19.4-fs<sub>RMS</sub> Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing.
IEEE J. Solid State Circuits, May, 2026
2025
An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier.
IEEE Trans. Very Large Scale Integr. Syst., October, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2022
An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs<sub>rms</sub> Jitter and Fast Frequency Hopping.
IEEE Trans. Very Large Scale Integr. Syst., 2022
2021
Microelectron. J., 2021
2020
Ultrawideband Power-Switchable Transmitter With 17.7-dBm Output Power for See-Through-Wall Radar.
IEEE Trans. Very Large Scale Integr. Syst., 2020