Chenjia Xie

According to our database, Chenjia Xie authored at least 13 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory.

Chenjia Xie, Zhuang Shao, Mingzhe Zhang, Yuan Du, Li Du

IEEE J. Solid State Circuits, October, 2025

A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations.

Chenjia Xie, Zhuang Shao, Ning Zhao, Xingyuan Hu, Yuan Du, Li Du

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

KV Cache Compression Based on Token-Level Redundancy Elimination and Bit-Level Encoding.

Tianze Li, Chenjia Xie, Jiayuan Chen, Yuan Du, Li Du

Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

2024

An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction.

Chenjia Xie, Zhuang Shao, Zhichao Chen, Yuan Du, Li Du

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

An Efficient GCN Accelerator Based on Workload Reorganization and Feature Reduction.

Zhuang Shao, Chenjia Xie, Zihan Ning, Qi Wu, Liang Chang, Yuan Du, Li Du

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

A Streaming Transformer Accelerator with Efficient On-Chip Normalization.

Ning Zhao, Jiayuan Chen, Jingjing Lv, Chenjia Xie, Yuan Du, Li Du

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling.

Chengrui Li, Ning Zhao, Xiaopeng Zhang, Wei Gao, Chenjia Xie, Yuan Du, Li Du

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2023

An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression.

Chenjia Xie, Zhuang Shao, Ning Zhao, Yuan Du, Li Du

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

Graph Neural Network Assisted S-Parameter Inference and Control-Word Generation of Terahertz Reconfigurable Intelligent Surface.

Zihan Ning, Tong Sun, Jizhao Li, Yanfei Ren, Chenjia Xie, Li Du, Lianggong Wen, Yuan Du

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators.

Hang Xu, Chenjia Xie, Xin Lu, Li Du, Yuan Du

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression.

Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access.

Xingyuan Hu, Zhuang Shao, Chenjia Xie, Li Du, Yuan Du

Proceedings of the 19th International SoC Design Conference, 2022

Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting.

Chenjia Xie, Zhuang Shao, Hang Xu, Xiaoliang Chen, Li Du, Yuan Du, Zhongfeng Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022