Zhongfeng Wang
Orcid: 0000-0002-7227-4786Affiliations:
- Nanjing University, School of Electronic Science and Engineering, Nanjing, China
- Broadcom Corporation, San Jose, CA, USA (former)
- Oregon State University, Corvallis, OR, USA (former)
- University of Minnesota, Minneapolis, MN, USA (former, PhD 2000)
According to our database1,
Zhongfeng Wang
authored at least 319 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024
Low-Latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection.
IEEE Internet Things J., April, 2024
Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins.
ACM Trans. Design Autom. Electr. Syst., March, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
Correlated Channel-Oriented Expectation Propagation-Based Detector for Massive MIMO Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
IEEE Trans. Computers, February, 2024
NASA-F: FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
IEEE Commun. Lett., January, 2024
An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT.
CoRR, 2024
An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes.
CoRR, 2024
CoRR, 2024
2023
An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
ProMiSE: A High-Performance Programmable Hardware Monitor for High Security Enforcement of Software Execution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization.
IEEE Trans. Neural Networks Learn. Syst., October, 2023
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
A Unified Acceleration Solution Based on Deformable Network for Image Pixel Processing.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
Automatic Model-Based Dataset Generation for High-Level Vision Tasks of Autonomous Driving in Haze Weather.
IEEE Trans. Ind. Informatics, August, 2023
Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm.
IEEE Trans. Neural Networks Learn. Syst., June, 2023
IEEE Trans. Computers, June, 2023
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
IEEE Commun. Lett., April, 2023
AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
IEEE Commun. Lett., January, 2023
IEEE Trans. Signal Process., 2023
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design.
ACM Trans. Design Autom. Electr. Syst., 2023
Intelligent Typography: Artistic Text Style Transfer for Complex Texture and Structure.
IEEE Trans. Multim., 2023
Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
An Efficient Accelerator Based on Lightweight Deformable 3D-CNN for Video Super-Resolution.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
NASA+: Neural Architecture Search and Acceleration for Multiplication-Reduced Hybrid Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network.
CoRR, 2023
Efficient N: M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design.
CoRR, 2023
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge.
CoRR, 2023
S2R: Exploring a Double-Win Transformer-Based Framework for Ideal and Blind Super-Resolution.
CoRR, 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attention.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2022
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Rethinking Adaptive Computing: Building a Unified Model Complexity-Reduction Framework With Adversarial Robustness.
IEEE Trans. Neural Networks Learn. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
High-Throughput LDPC-CC Decoders Based on Storage, Arithmetic, and Control Improvements.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Efficient Software Implementation of the SIKE Protocol Using a New Data Representation.
IEEE Trans. Computers, 2022
RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity.
IEEE Trans. Computers, 2022
Neural Comput. Appl., 2022
LDPC decoding with locally informed dynamic scheduling based on the law of large numbers.
IET Commun., 2022
IEEE Commun. Lett., 2022
EURASIP J. Adv. Signal Process., 2022
CoRR, 2022
IEEE Access, 2022
Proceedings of the 14th International Conference on Wireless Communications and Signal Processing, 2022
Proceedings of the Arithmetic of Finite Fields - 9th International Workshop, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
An Efficient Accelerator of Deformable 3D Convolutional Network for Video Super-Resolution.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Magical-Decomposition: Winning Both Adversarial Robustness and Efficiency on Hardware.
Proceedings of the International Conference on Machine Learning and Cybernetics, 2022
NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2022, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Low-Complexity Dynamic Single-Minimum Min-Sum Algorithm and Hardware Implementation for LDPC Codes.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Low-Complexity Parallel Syndrome Computation for BCH Decoders Based on Cyclotomic FFT.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the 27th Asia Pacific Conference on Communications, 2022
Proceedings of the 27th Asia Pacific Conference on Communications, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter.
J. Signal Process. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Computers, 2021
IEEE Commun. Lett., 2021
An Improved Method for Performance Analysis of Generalized Integrated Interleaved Codes.
IEEE Commun. Lett., 2021
IACR Cryptol. ePrint Arch., 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator.
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
Proceedings of the IEEE International Conference on Acoustics, 2021
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
Federated Regularization Learning: an Accurate and Safe Method for Federated Learning.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A lightweight face detector by integrating the convolutional neural network with the image pyramid.
Pattern Recognit. Lett., 2020
Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data.
IEICE Electron. Express, 2020
Faster Software Implementation of the SIKE Protocol Based on A New Data Representation.
IACR Cryptol. ePrint Arch., 2020
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2020
A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing.
IEEE Access, 2020
Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Temporal Residual Feature Learning for Efficient 3D Convolutional Neural Network on Action Recognition Task.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
An Implementation of Pre-Quantized Random Demodulator Based on Amplitude-to-Pulse Converter.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base".
IEEE Trans. Very Large Scale Integr. Syst., 2019
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs.
IEICE Electron. Express, 2019
IEEE Commun. Lett., 2019
IACR Cryptol. ePrint Arch., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm.
CoRR, 2019
IEEE Access, 2019
Improved Decoding Algorithms of LDPC Codes Based on Reliability Metrics of Variable Nodes.
IEEE Access, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
CLA Formula Aided Fast Architecture Design for Clustered Look-Ahead Pipelined IIR Digital Filter.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes.
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 2019 IEEE International Conference on Communications, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 25th Asia-Pacific Conference on Communications, 2019
2018
IEEE Wirel. Commun. Lett., 2018
J. Signal Process. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Commun., 2018
An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Signal Process. Lett., 2018
Microelectron. J., 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Fast and Low-Complexity Decoding Algorithm and Architecture for Quadruple-Error-Correcting RS codes.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Image Process., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
Guest Editorial Advanced Baseband Processing Circuits and Systems for 5G Communications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
IEEE Commun. Stand. Mag., 2017
Proceedings of the 9th International Conference on Wireless Communications and Signal Processing, 2017
Proceedings of the 9th International Conference on Wireless Communications and Signal Processing, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Algorithm and architecture for joint detection and decoding for MIMO with LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Circuits Syst. Signal Process., 2016
Proceedings of the 8th International Conference on Wireless Communications & Signal Processing, 2016
Proceedings of the 8th International Conference on Wireless Communications & Signal Processing, 2016
Compressed Power Spectral Density Estimation via Group-Based Total Variation Minimization.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IET Commun., 2011
Proceedings of the International SoC Design Conference, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Consumer Electron., 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Factorization Architecture by Direct Root Computation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
Proceedings of the IEEE International Conference on Acoustics, 2007
2006
High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Study of Early Stopping Criteria for Turbo Decoding and Their Applications in WCDMA Systems.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004