Chi-Hsiang Weng

According to our database1, Chi-Hsiang Weng authored at least 1 paper in 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2018
Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018


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