Yu-Der Chih

According to our database1, Yu-Der Chih authored at least 24 papers between 2011 and 2020.

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Bibliography

2020
An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.
IEEE J. Solid State Circuits, 2019

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation.
IEEE J. Solid State Circuits, 2019

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.
IEEE J. Solid State Circuits, 2019

2018
A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 1.4Mb 40-nm embedded ReRAM macro with 0.07um<sup>2</sup> bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.
IEEE J. Solid State Circuits, 2015

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros.
IEEE J. Solid State Circuits, 2015

2014
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits, 2014

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro.
IEEE J. Solid State Circuits, 2013

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013

A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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