Chung-Cheng Chou
According to our database1,
Chung-Cheng Chou
authored at least 4 papers
between 2018 and 2024.
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Bibliography
2024
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2020
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2018
An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018