Chin-I Su
According to our database1,
Chin-I Su
authored at least 9 papers
between 2016 and 2023.
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Bibliography
2023
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices.
IEEE J. Solid State Circuits, 2023
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator.
IEEE J. Solid State Circuits, 2021
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2018
Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2016
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016