Chi W. Yau

According to our database1, Chi W. Yau authored at least 10 papers between 1986 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

1996
Lessons Learned from Practical Applications of BIST/B-S Technology.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1993
A structured approach to board-level BIST using the boundary-scan master.
Microprocess. Microsystems, 1993

1992
A Framework for Boundary-Scan Based System Test Diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Achieving Board-Level BIST Using the Boundary-Scan Master.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
The boundary-scan master: target applications and functional requirements.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects.
Proceedings of the Proceedings International Test Conference 1989, 1989

A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects.
Proceedings of the Proceedings International Test Conference 1989, 1989

An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
Trouble-Shooting: A Key to Process Improvement.
Proceedings of the Proceedings International Test Conference 1988, 1988

1986
Concurrent Test Generation Using AI Techniques.
Proceedings of the Proceedings International Test Conference 1986, 1986


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