Najmi T. Jarwala

According to our database, Najmi T. Jarwala authored at least 12 papers between 1988 and 1997.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1997

Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.

Najmi T. Jarwala

J. Electron. Test., 1997

1996

Built-In Self-Test: Assuring System Integrity.

Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie

Computer, 1996

Hardware-Software Co-Design for Test: It's the Last Straw!

J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Lessons Learned from Practical Applications of BIST/B-S Technology.

Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus.

Wuudiann Ke, Duy Le, Najmi T. Jarwala

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1993

A structured approach to board-level BIST using the boundary-scan master.

Najmi T. Jarwala, Chi W. Yau

Microprocess. Microsystems, 1993

1992

A Framework for Boundary-Scan Based System Test Diagnosis.

Najmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Achieving Board-Level BIST Using the Boundary-Scan Master.

Najmi T. Jarwala, Chi W. Yau

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

The boundary-scan master: target applications and functional requirements.

Chi W. Yau, Najmi T. Jarwala

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects.

Najmi T. Jarwala, Chi W. Yau

Proceedings of the Proceedings International Test Conference 1989, 1989

A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects.

Najmi T. Jarwala, Chi W. Yau

Proceedings of the Proceedings International Test Conference 1989, 1989

1988

TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.

Najmi T. Jarwala, Dhiraj K. Pradhan

IEEE Trans. Computers, 1988