Shianling Wu

According to our database, Shianling Wu authored at least 24 papers between 1985 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang

ACM Trans. Design Autom. Electr. Syst., 2012

Physical-design-friendly hierarchical logic built-in self-test - A case study.

Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

CSER: BISER-based concurrent soft-error resilience.

Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.

Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Turbo1500: Core-Based Design for Test and Diagnosis.

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li

IEEE Des. Test Comput., 2009

Logic BIST Architecture for System-Level Test and Diagnosis.

Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Analysis of Resistive Bridging Defects in a Synchronizer.

Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu

IEEE Des. Test Comput., 2008

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li

Proceedings of the 2008 IEEE International Test Conference, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.

Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Practical Challenges in Logic BIST Implementation.

Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2006

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.

Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Test compression and logic BIST at your fingertips.

Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.

Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

At-Speed Logic BIST Architecture for Multi-Clock Designs.

Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

At-Speed Logic BIST for IP Cores.

B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu

Proceedings of the 2005 Design, 2005

2004

VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.

Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2000

Collaboration between Industry and Academia in Test Research.

Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1998

A non-enumerative path delay fault simulator for sequential circuits.

Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996

Lessons Learned from Practical Applications of BIST/B-S Technology.

Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1985

A Sequential Circuit Test Generation System.

Sivanarayana Mallela, Shianling Wu

Proceedings of the Proceedings International Test Conference 1985, 1985