Chia-I Chen

According to our database, Chia-I Chen authored at least 8 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

GRAde: a long-read sequencing approach to efficiently identifying the CYP11B1/CYP11B2 chimeric form in patients with glucocorticoid-remediable aldosteronism.

Yu-Ching Wu, Chia-I Chen, Peng-Ying Chen, Chun-Hung Kuo, Yi-Hsuan Hung, Kang-Yung Peng, Vin-Cent Wu, Jyy-Jih Tsai-Wu, Chia-Lang Hsu

BMC Bioinform., 2021

2014

Apply high-level synthesis design and verification methodology on floating-point unit implementation.

Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2012

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay.

Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture.

Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family.

Chia-I Chen, Juinn-Dar Huang

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Architectural exploration of 3D FPGAs towards a better balance between area and delay.

Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication.

Chia-I Chen, Juinn-Dar Huang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009

CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture.

Chia-I Chen, Juinn-Dar Huang

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009