Jing-Yang Jou

According to our database1, Jing-Yang Jou authored at least 115 papers between 1988 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to the computer aided design of digital circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2016
Wave digital filter based analog circuit emulation on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Resource-aware functional ECO patch generation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Chain-based pin count minimization for general-purpose digital microfluidic biochips.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors.
ACM Trans. Embed. Comput. Syst., 2015

A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs.
IEEE Trans. Computers, 2015

Power-Efficient Instancy Aware DRAM Scheduling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2014

Reducing Contention in Shared Last-Level Cache for Throughput Processors.
ACM Trans. Design Autom. Electr. Syst., 2014

Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog.
ACM Trans. Design Autom. Electr. Syst., 2014

Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors.
J. Inf. Sci. Eng., 2014

ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A learning-on-cloud power management policy for smart devices.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A read-write aware DRAM scheduling for power reduction in multi-core systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A formal method to improve SystemVerilog functional coverage.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Thread affinity mapping for irregular data access on shared Cache GPGPU.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Design-for-debug layout adjustment for FIB probing and circuit editing.
Proceedings of the 2011 IEEE International Test Conference, 2011

Mixed non-rectangular block packing for non-Manhattan layout architectures.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Equivalence checking of scheduling with speculative code transformations in high-level synthesis.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
FSM-Based Formal Compliance Verification of Interface Protocols.
J. Inf. Sci. Eng., 2010

Expandable MDC-based FFT architecture and its generator for high-performance applications.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Unleash the parallelism of 3DIC partitioning on GPGPU.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2009

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Multiple-Fault Diagnosis Using Faulty-Region Identification.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008
Verification of Pin-Accurate Port Connections.
IEEE Des. Test Comput., 2008

Crosstalk-avoidance coding for low-power on-chip bus.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Observability Analysis on HDL Descriptions for Effective Functional Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hybrid Wordlength Optimization Methods of Pipelined FFT Processors.
IEEE Trans. Computers, 2007

A Tableless Approach for High-Level Power Modeling Using Neural Networks.
J. Inf. Sci. Eng., 2007

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Reliable crosstalk-driven interconnect optimization.
ACM Trans. Design Autom. Electr. Syst., 2006

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.
IEEE Trans. Computers, 2006

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

FSM-based transaction-level functional coverage for interface compliance verification.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
An efficient heterogeneous tree multiplexer synthesis technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An optimum algorithm for compacting error traces for efficient functional debugging.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Simultaneous floor plan and buffer-block optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation.
IEEE Des. Test Comput., 2004

Verification on Port Connections.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

RLC effects on worst-case switching pattern for on-chip buses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An efficient approach for hierarchical submodule extraction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An efficient logic extraction algorithm using partitioning and circuit encoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Graph Automorphism-Based Algorithm for Determining Symmetric Inputs.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Enhancing sequential depth computation with a branch-and-bound algorithm.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Layout techniques for on-chip interconnect inductance reduction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

On compliance test of on-chip bus for SOC.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A Design-for-Verification Technique for Functional Pattern Reduction.
IEEE Des. Test Comput., 2003

SoC design integration by using automatic interconnection rectification.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An efficient approach for error diagnosis in HDL design.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An automatic interconnection rectification technique for SoC design integration.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Simultaneous floorplanning and buffer block planning.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

An efficient IP-level power model for complex digital circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation.
J. Circuits Syst. Comput., 2002

A Practical Approach to Cycle Bound Estimation for Property Checking.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Effective Error Diagnosis for RTL Designs in HDLs.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Unified functional decomposition via encoding for FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Automatic Functional Vector Generation Using the Interacting FSM Model.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

An AVPG for SOC design verification with port order fault model.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On tri-state buffer inference in HDL synthesis.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Grouped input power sensitive transition an input sequence compaction technique for power estimation.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On placement and routing of wafer scale memory.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

An efficient design-for-verification technique for HDLs.
Proceedings of ASP-DAC 2001, 2001

2000
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2000

On computing the minimum feedback vertex set of a directed graph bycontraction operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

An Automatic Controller Extractor for HDL Descriptions at the RTL.
IEEE Des. Test Comput., 2000

Optimal reliable crosstalk-driven interconnect optimization.
Proceedings of the 2000 International Symposium on Physical Design, 2000

A novel approach for functional coverage measurement in HDL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Collaboration between Industry and Academia in Test Research.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A new method for constructing IP level power model based on power sensitivity.
Proceedings of ASP-DAC 2000, 2000

1999
A structure-oriented power modeling technique for macrocells.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Two-level logic minimization for low power.
ACM Trans. Design Autom. Electr. Syst., 1999

An Efficient Functional Coverage Test for HDL Descriptions at RTL.
Proceedings of the IEEE International Conference On Computer Design, 1999

Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD.
Proceedings of the IEEE International Conference On Computer Design, 1999

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.
Proceedings of the 36th Conference on Design Automation, 1999

Hierarchical Floorplan Design on the Internet.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
On circuit clustering for area/delay tradeoff under capacity and pin constraints.
IEEE Trans. Very Large Scale Integr. Syst., 1998

A Logical Fault Model for Library Coherence Checking.
J. Inf. Sci. Eng., 1998

Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.
Proceedings of the 35th Conference on Design Automation, 1998

Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Power Driven Partial Scan.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

A power modeling and characterization method for macrocells using structure information.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A power driven two-level logic optimizer.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

BDD based lambda set selection in Roth-Karp decomposition for LUT architecture.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
A power modeling and characterization method for the CMOS standard cell library.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Easily Testable Data Path Allocation Using Input/Output Registers.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

An Efficient PRPG Strategy By Utilizing Essential Faults.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
Timing-Driven Partial Scan.
IEEE Des. Test Comput., 1995

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

An effective BIST design for PLA.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1992
A functional fault model for sequential machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1990
Functional test generation for finite state machines.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

A Single-State-Transition Fault Model for Sequential Machines.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1988
Fault-Tolerant FFT Networks.
IEEE Trans. Computers, 1988

Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing.
Proceedings of the International Conference on Parallel Processing, 1988

BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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