Chi-Feng Wu

According to our database1, Chi-Feng Wu authored at least 27 papers between 1999 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Apply high-level synthesis design and verification methodology on floating-point unit implementation.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Mask-cost-aware ECO routing<sup>∗</sup>.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Case study of yield learning through in-house flow of volume diagnosis.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Applying a Functional Neurofuzzy Network to Real-Time Lane Detection and Front-Vehicle Distance Measurement.
IEEE Trans. Syst. Man Cybern. Part C, 2012

Locating Text in Images Based on the Smooth Gray-Level Detection.
Int. J. Image Graph., 2012

Test for more than pass/fail using on-chip temperature sensor.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A functional neural fuzzy network for classification applications.
Expert Syst. Appl., 2011

Application of neural networks and genetic algorithms to the screening for high quality chips.
Appl. Soft Comput., 2009

A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design.
Proceedings of the 2009 IEEE International Test Conference, 2009

A novel approach to enable decorrelating multiuser detection without matrix inversion operations.
Int. J. Commun. Syst., 2004

Isotropic air-interface technologies for fourth generation wireless communications.
Wirel. Commun. Mob. Comput., 2003

Built-in redundancy analysis for memory yield improvement.
IEEE Trans. Reliab., 2003

Fault simulation and test algorithm generation for random accessmemories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.
J. Electron. Test., 2002

Image Processing Techniques for Wafer Defect Cluster Identification.
IEEE Des. Test Comput., 2002

Flash Memory Built-In Self-Test Using March-Like Algorithm.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.
Proceedings of the 38th Design Automation Conference, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Testing and Diagnosing Dynamic Reconfigurable FPGA.
VLSI Design, 2000

Simulation-Based Test Algorithm Generation for Random Access Memories.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Error Catch and Analysis for Semiconductor Memories Using March Tests.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A built-in self-test and self-diagnosis scheme for embedded SRAM.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Collaboration between Industry and Academia in Test Research.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A Programmable BIST Core for Embedded DRAM.
IEEE Des. Test Comput., 1999

RAMSES: A Fast Memory Fault Simulator.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Testing Interconnects of Dynamic Reconfigurable FPGAs.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999