Chien-Chung Tsai

According to our database, Chien-Chung Tsai authored at least 16 papers between 1993 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2003

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.

Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

Synthesis of Scan Chains for Netlist Descriptions at RT-Level.

Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy

J. Electron. Test., 2002

On Concurrent Test of Core-Based SOC Design.

Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy

J. Electron. Test., 2002

Constraint Driven Pin Mapping for Concurrent SOC Testing.

Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.

Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

On RTL scan design.

Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Effect of RTL coding style on testability.

Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.

Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1998

A novel combinational testability analysis by considering signal correlation.

Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Boolean Functions Classification via Fixed Polarity Reed-Muller Forms.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 1997

1996

Generalized Reed-Muller Forms as a Tool to Detect Symmetries.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 1996

Logic Synthesis for Testability.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Multilevel Logic Synthesis for Arithmetic Functions.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 33st Conference on Design Automation, 1996

1994

Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Boolean Matching Using Generalized Reed-Muller Forms.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 31st Conference on Design Automation, 1994

1993

Efficient minimization algorithms for fixed polarity AND/XOR canonical networks.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993