Sudhakar M. Reddy

Affiliations:
  • University of Iowa, Iowa City, IA, USA


According to our database1, Sudhakar M. Reddy authored at least 632 papers between 1968 and 2022.

Collaborative distances:

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Bibliography

2022
Efficient Test Compression Configuration Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2020
Deterministic Stellar BIST for Automotive ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

LFSR generation for high test coverage and low hardware overhead.
IET Comput. Digit. Tech., 2020

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
Proceedings of the IEEE International Test Conference, 2020

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
Proceedings of the IEEE International Test Conference in Asia, 2020

Efficient Prognostication of Pattern Count with Different Input Compression Ratios.
Proceedings of the IEEE European Test Symposium, 2020

2019
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.
ACM Trans. Design Autom. Electr. Syst., 2019

A supervised machine learning application in volume diagnosis.
Proceedings of the 24th IEEE European Test Symposium, 2019

On Generating Fault Diagnosis Patterns for Designs with X Sources.
Proceedings of the 24th IEEE European Test Symposium, 2019

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Deep Learning Based Test Compression Analyzer.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
A Repair-for-Diagnosis Methodology for Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Staggered ATPG with capture-per-cycle observation test points.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Deterministic Stellar BIST for In-System Automotive Test.
Proceedings of the IEEE International Test Conference, 2018

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run.
Proceedings of the IEEE International Test Conference, 2018

Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run.
Proceedings of the IEEE International Test Conference in Asia, 2018

Recycled IC detection through aging sensor.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Embedded Deterministic Test Points.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Efficient SAT-based generation of hazard-activated TSOF tests.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Test generation for open and delay faults in CMOS circuits.
Proceedings of the International Test Conference in Asia, 2017

Volume diagnosis data mining.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Minimal area test points for deterministic patterns.
Proceedings of the 2016 IEEE International Test Conference, 2016

Transistor stuck-on fault detection tests for digital CMOS circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016

On the Switching Activity in Faulty Circuits During Test Application.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Isometric Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Improving diagnosis resolution of a fault detection test set.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement.
Proceedings of the 28th International Conference on VLSI Design, 2015

On generating high quality tests based on cell functions.
Proceedings of the 2015 IEEE International Test Conference, 2015

2014
On achieving minimal size test sets for scan designs.
it Inf. Technol., 2014

Efficient SAT-Based Circuit Initialization for Larger Designs.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A Cube-Aware Compaction Method for Scan ATPG.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

SAT-Based Test Pattern Generation with Improved Dynamic Compaction.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Isometric test compression with low toggling activity.
Proceedings of the 2014 International Test Conference, 2014

Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Fundamentals of Small-Delay Defect Testing.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2013
Distributed dynamic partitioning based diagnosis of scan chain.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

On the generation of compact test sets.
Proceedings of the 2013 IEEE International Test Conference, 2013

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Resolution of Diagnosis Based on Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Reset and partial-reset-based functional broadside tests.
IET Comput. Digit. Tech., 2012

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.
Proceedings of the 25th International Conference on VLSI Design, 2012

Functional test of small-delay faults using SAT and Craig interpolation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Improved volume diagnosis throughput using dynamic design partitioning.
Proceedings of the 2012 IEEE International Test Conference, 2012

TSV and DFT cost aware circuit partitioning for 3D-SOCs.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Performance aware partitioning for 3D-SOCs.
Proceedings of the International SoC Design Conference, 2012

Session Summary III: Power-Aware Testing: Present and Future.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Static Test Data Volume Reduction Using Complementation or Modulo- M Addition.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Broadside and Functional Broadside Tests for Partial-Scan Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

On Functional Broadside Tests With Functional Propagation Conditions.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Fixed-State Tests for Delay Faults in Scan Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Reducing the switching activity of test sequences under transparent-scan.
ACM Trans. Design Autom. Electr. Syst., 2011

Modeling and Mitigating Transient Errors in Logic Circuits.
IEEE Trans. Dependable Secur. Comput., 2011

Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan.
J. Low Power Electron., 2011

Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation.
IET Comput. Digit. Tech., 2011

Sizes of test sets for path delay faults using strong and weak non-robust tests.
IET Comput. Digit. Tech., 2011

Two-dimensional partially functional broadside tests.
IET Comput. Digit. Tech., 2011

Primary input cones based on test sequences in synchronous sequential circuits.
IET Comput. Digit. Tech., 2011

Low power compression utilizing clock-gating.
Proceedings of the 2011 IEEE International Test Conference, 2011

Genetic algorithm based approach for segmented testing.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Max-Fill: A method to generate high quality delay tests.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing.
Proceedings of the Design, Automation and Test in Europe, 2011

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

On Using Design Partitioning to Reduce Diagnosis Memory Footprint.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Fault diagnosis aware ATE assisted test response compaction.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Switching Activity as a Test Compaction Heuristic for Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Robust Fault Models Where Undetectable Faults Imply Logic Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Path Selection for Transition Path Delay Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests.
IEEE Trans. Very Large Scale Integr. Syst., 2010

On Undetectable Faults and Fault Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On Test Generation With Test Vector Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

TOV: Sequential Test Generation by Ordering of Test Vectors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.
IEEE Trans. Computers, 2010

Test Sequences with Reduced and Increased Switching Activity.
J. Low Power Electron., 2010

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.
Int. J. Parallel Program., 2010

Static test compaction for diagnostic test sets of full-scan circuits.
IET Comput. Digit. Tech., 2010

Diagnosis of path delay faults based on low-coverage tests.
IET Comput. Digit. Tech., 2010

On multiple bridging faults.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Forming multi-cycle tests for delay faults by concatenating broadside tests.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

At-speed scan test with low switching activity.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Output-Dependent Diagnostic Test Generation.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Low capture power at-speed test in EDT environment.
Proceedings of the 2011 IEEE International Test Conference, 2010

Multiple fault activation cycle tests for transistor stuck-open faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Selecting state variables for improved on-line testability through output response comparison of identical circuits.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Deterministic broadside test generation for transition path delay faults.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Input test data volume reduction based on test vector chains.
Proceedings of the 15th European Test Symposium, 2010

Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

On reset based functional broadside tests.
Proceedings of the Design, Automation and Test in Europe, 2010

Reducing the storage requirements of a test sequence by using a background vector.
Proceedings of the Design, Automation and Test in Europe, 2010

Diagnosis of Multiple Physical Defects Using Logic Fault Models.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

On Bias in Transition Coverage of Test Sets for Path Delay Faults.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Functional and partially-functional skewed-load tests.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Random Test Generation With Input Cube Avoidance.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits.
ACM Trans. Design Autom. Electr. Syst., 2009

Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits.
IEEE Trans. Dependable Secur. Comput., 2009

Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Diagnosis of Multiple-Voltage Design With Bridge Defect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Process Variation-Aware Test for Resistive Bridges.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Test compaction methods for transition faults under transparent-scan.
IET Comput. Digit. Tech., 2009

Test vector chains for increasing the fault coverage and numbers of detections.
IET Comput. Digit. Tech., 2009

Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution.
IET Comput. Digit. Tech., 2009

Definition and generation of partially-functional broadside tests.
IET Comput. Digit. Tech., 2009

The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Markov source based test length optimized SCAN-BIST architecture.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

State persistence: a property for guiding test generation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Definition and application of approximate necessary assignments.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Partitioned n-detection test generation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation.
Proceedings of the 14th IEEE European Test Symposium, 2009

Improving the Detectability of Resistive Open Faults in Scan Cells.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

On-chip Generation of the Second Primary Input Vectors of Broadside Tests.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Improving compressed test pattern generation for multiple scan chain failure diagnosis.
Proceedings of the Design, Automation and Test in Europe, 2009

A scalable method for the generation of small test sets.
Proceedings of the Design, Automation and Test in Europe, 2009

On Improving Diagnostic Test Generation for Scan Chain Failures.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fault Diagnosis under Transparent-Scan.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Dynamic Compaction in SAT-Based ATPG.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

N-distinguishing Tests for Enhanced Defect Diagnosis.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Detectability of internal bridging faults in scan chains.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Dynamic test compaction for a random test generation procedure with input cube avoidance.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.
IEEE Trans. Very Large Scale Integr. Syst., 2008

On the Saturation of n-Detection Test Generation by Different Definitions With Increased n.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

On Complete Functional Broadside Tests for Transition Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Functional Broadside Tests with Minimum and Maximum Switching Activity.
J. Low Power Electron., 2008

On Detection of Bridge Defects with Stuck-at Tests.
IEICE Trans. Inf. Syst., 2008

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Synthesis for Broadside Testability of Transition Faults.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

On Common-Mode Skewed-Load and Broadside Tests.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Detection of Internal Stuck-open Faults in Scan Chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

An Enhanced Logic BIST Architecture for Online Testing.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Safe Fault Collapsing Based on Dominance Relations.
Proceedings of the 13th European Test Symposium, 2008

Bridge Defect Diagnosis for Multiple-Voltage Design.
Proceedings of the 13th European Test Symposium, 2008

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

On Reducing Circuit Malfunctions Caused by Soft Errors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy.
Proceedings of the Design, Automation and Test in Europe, 2008

On tests to detect via opens in digital CMOS circuits.
Proceedings of the 45th Design Automation Conference, 2008

Hyperactive Faults Dictionary to Increase Diagnosis Throughput.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Test vector chains for increased targeted and untargeted fault coverage.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Forming N-detection test sets without test generation.
ACM Trans. Design Autom. Electr. Syst., 2007

Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints.
ACM Trans. Design Autom. Electr. Syst., 2007

z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Enhancing delay fault coverage through low-power segmented scan.
IET Comput. Digit. Tech., 2007

Effectiveness of scan-based delay fault tests in diagnosis of transition faults.
IET Comput. Digit. Tech., 2007

Worst-case and average-case analysis of n-detection test sets and test generation strategies.
IET Comput. Digit. Tech., 2007

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits.
Electron. Notes Theor. Comput. Sci., 2007

Scan-Based Tests with Low Switching Activity.
IEEE Des. Test Comput., 2007

Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Low Shift and Capture Power Scan Tests.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Functional Broadside Tests with Different Levels of Reachability.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Faster defect localization in nanometer technology based on defective cell diagnosis.
Proceedings of the 2007 IEEE International Test Conference, 2007

On the saturation of n-detection test sets with increased n.
Proceedings of the 2007 IEEE International Test Conference, 2007

Interconnect open defect diagnosis with minimal physical information.
Proceedings of the 2007 IEEE International Test Conference, 2007

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Diagnostic Test Generation Based on Subsets of Faults.
Proceedings of the 12th European Test Symposium, 2007

Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A-Diagnosis: A Complement to Z-Diagnosis.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

On test generation by input cube avoidance.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Improved n-Detection Test Sequences Under Transparent Scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Using Dummy Bridging Faults to Define Reduced Sets of Target Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Generation of Functional Broadside Tests for Transition Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.
IEEE Trans. Computers, 2006

Scan Tests with Multiple Fault Activation Cycles for Delay Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Dominance Based Analysis for Large Volume Production Fail Diagnosis.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

On Methods to Improve Location Based Logic Diagnosis.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.
Proceedings of the 2006 IEEE International Test Conference, 2006

Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A delay fault model for at-speed fault simulation and test generation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Fault Collapsing for Transition Faults Using Extended Transition Faults.
Proceedings of the 11th European Test Symposium, 2006

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
Proceedings of the 11th European Test Symposium, 2006

Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Test Generation for Open Defects in CMOS Circuits.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Test compaction for transition faults under transparent-scan.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A test pattern ordering algorithm for diagnosis with truncated fail data.
Proceedings of the 43rd Design Automation Conference, 2006

Cache size selection for performance, energy and reliability of time-constrained systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Autoscan: a scan design without external scan inputs or outputs.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors.
IEEE Trans. Dependable Secur. Comput., 2005

Finite memory test response compactors for embedded test applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On fault equivalence, fault dominance, and incompletely specified test sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On reducing test application time for scan circuits using limited scan operations and transfer sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Full-speed field programmable memory BIST supporting multi-level looping.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Forming N-detection test sets from one-detection test sets without test generation.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Full-speed field-programmable memory BIST architecture.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Methods for improving transition delay fault coverage using broadside tests.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Fault Diagnosis and Fault Model Aliasing.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

On Reducing Peak Current and Power during Test.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Dynamic Test Compaction for Bridging Faults.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Battery-aware dynamic voltage scaling in multiprocessor embedded system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Path-oriented transition fault test generation considering operating conditions.
Proceedings of the 10th European Test Symposium, 2005

Using dummy bridging faults to define a reduced set of target faults.
Proceedings of the 10th European Test Symposium, 2005

A unified fault model and test generation procedure for interconnect opens and bridges.
Proceedings of the 10th European Test Symposium, 2005

On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Recovery During Concurrent On-Line Testing of Identical Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Defect Aware Test Patterns.
Proceedings of the 2005 Design, 2005

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits.
Proceedings of the 2005 Design, 2005

Worst-Case and Average-Case Analysis of n-Detection Test Sets.
Proceedings of the 2005 Design, 2005

Bridge Defect Diagnosis with Physical Information.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

On Improving Defect Coverage of Stuck-at Fault Tests.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
IEEE Trans. Very Large Scale Integr. Syst., 2004

On the characterization and efficient computation of hard-to-detect bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Vector-restoration-based static compaction using random initial omission.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.
IEEE Trans. Computers, 2004

A Measure of Quality for n-Detection Test Sets.
IEEE Trans. Computers, 2004

On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
IEEE Trans. Computers, 2004

Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.
IEEE Trans. Computers, 2004

Don't Care Identification and Statistical Encoding for Test Data Compression.
IEICE Trans. Inf. Syst., 2004

Memory BIST Using ESP.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Scan BIST Targeting Transition Faults Using a Markov Source.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.
Proceedings of the 9th European Test Symposium, 2004

Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis.
Proceedings of the 2004 Design, 2004

Level of Similarity: A Metric for Fault Collapsing.
Proceedings of the 2004 Design, 2004

On test generation for transition faults with minimized peak power dissipation.
Proceedings of the 41th Design Automation Conference, 2004

Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Postprocessing Procedure of Test Enrichment for Path Delay Faults.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Properties of Maximally Dominating Faults.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Multiple Scan Tree Design with Test Vector Modification.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
On test data volume reduction for multiple scan chain designs.
ACM Trans. Design Autom. Electr. Syst., 2003

Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Test data compression based on input-output dependence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Theorems for identifying undetectable faults in partial-scan circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Test enrichment for path delay faults using multiple sets of target faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

PROPTEST: a property-based test generator for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Reverse-order-restoration-based static test compaction for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

On Selecting Testable Paths in Scan Designs.
J. Electron. Test., 2003

A Low Power Pseudo-Random BIST Technique.
J. Electron. Test., 2003

SOC Test Scheduling Using Simulated Annealing.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Test Interface for Built-In Test of Non-Isolated Scanned Cores.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Optimizing SOC Test Resources Using Dual Sequences.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Convolutional Compaction of Test Responses.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

An Improved Markov Source Design for Scan BIST.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Static Test Compaction for Multiple Full-Scan Circuits.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

On Compacting Test Response Data Containing Unknown Values.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

On path selection for delay fault testing considering operating conditions [logic IC testing].
Proceedings of the 8th European Test Workshop, 2003

On the Characterization of Hard-to-Detect Bridging Faults.
Proceedings of the 2003 Design, 2003

Test Data Compression Based on Output Dependence.
Proceedings of the 2003 Design, 2003

A New Approach to Test Generation and Test Compaction for Scan Circuits.
Proceedings of the 2003 Design, 2003

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.
Proceedings of the 2003 Design, 2003

On test data compression and n-detection test sets.
Proceedings of the 40th Design Automation Conference, 2003

A scan BIST generation method using a markov source and partial bit-fixing.
Proceedings of the 40th Design Automation Conference, 2003

Test Data Volume Reduction by Test Data Realignment.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A DFT Approach for Path Delay Faults in Interconnected Circuits.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Testing Delay Faults in Embedded CAMs.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
n-pass n-detection fault simulation and its applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.
IEEE Trans. Computers, 2002

Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission.
IEEE Trans. Computers, 2002

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times.
IEEE Trans. Computers, 2002

Synthesis of Scan Chains for Netlist Descriptions at RT-Level.
J. Electron. Test., 2002

On Concurrent Test of Core-Based SOC Design.
J. Electron. Test., 2002

Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Constraint Driven Pin Mapping for Concurrent SOC Testing.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Pseudo Random Patterns Using Markov Sources for Scan BIST.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Don't-Care Identification on Specific Bits of Test Patterns.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Conflict driven techniques for improving deterministic test pattern generation.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

On undetectable faults in partial scan circuits.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

A Method of Static Test Compaction Based on Don't Care Identification.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Data Compression Using Don't-Care Identification and Statistical Encoding.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Finding a Common Fault Response for Diagnosis during Silicon Debug.
Proceedings of the 2002 Design, 2002

On output response compression in the presence of unknown output values.
Proceedings of the 39th Design Automation Conference, 2002

On Generating High Quality Tests for Transition Faults.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Data Compression Using Don?t-Care Identification and Statistical Encoding.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Core - Clustering Based SOC Test Scheduling Optimization.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.
IEEE Trans. Very Large Scale Integr. Syst., 2001

A built-in self-test method for diagnosis of synchronous sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Forward-looking fault simulation for improved static compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

On diagnosis and diagnostic test generation for pattern-dependenttransition faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Vector replacement to improve static-test compaction forsynchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits.
J. Syst. Archit., 2001

On the Use of Fault Dominance in n-Detection Test Generation.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

On Improving Static Test Compaction for Sequential Circuits.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

A method to enhance the fault coverage obtained by output response comparison of identical circuits.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

On static test compaction and test pattern ordering for scan designs.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

On RTL scan design.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

ITEM: an iterative improvement test generation procedure for synchronous sequential circuits.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Sequence reordering to improve the levels of compaction achievable by static compaction procedures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing.
Proceedings of the 38th Design Automation Conference, 2001

An Efficient Method to Identify Untestable Path Delay Faults.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
On synchronizable circuits and their synchronizing sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

On n-detection test sets and variable n-detection test sets fortransition faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Computers, 2000

On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.
IEEE Trans. Computers, 2000

On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines.
IEEE Trans. Computers, 2000

Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.
J. Electron. Test., 2000

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Test Transformation to Improve Compaction by Statistical Encoding.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Fault diagnosis based on parameters of output responses.
Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000

On validating data hold times for flip-flops in sequential circuits.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Selection of potentially testable path delay faults for test generation.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Simulation Based Test Generation for Scan Designs.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Improving the Proportion of At-Speed Tests in Scan BIST.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits.
Proceedings of the 5th European Test Workshop, 2000

Test-Point Insertion to Enhance Test Compaction for Scan Designs.
Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

Functional Test Generation for Full Scan Circuits.
Proceedings of the 2000 Design, 2000

Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits.
Proceedings of the 2000 Design, 2000

On diagnosis of pattern-dependent delay faults.
Proceedings of the 37th Conference on Design Automation, 2000

Reducing test application time for full scan circuits by the addition of transfer sequences.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

On the feasibility of fault simulation using partial circuit descriptions.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Enhanced untestable path analysis using edge graphs.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

High Performance/Delay Testing.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Universal delay test sets for logic networks.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Static test compaction for synchronous sequential circuits based on vector restoration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A comment on "Improving a nonenumerative method to estimate path delay fault coverage".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits.
IEEE Trans. Computers, 1999

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Flexible Path Selection Procedure for Path Delay Fault Testing.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

The effects of test compaction on fault diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Application of Tools Developed at the University of Iowa to ITC Benchmarks.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

On achieving complete coverage of delay faults in full scan circuits using locally available lines.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
Proceedings of the IEEE International Conference On Computer Design, 1999

An approach for improving the levels of compaction achieved by vector omission.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Techniques for improving the efficiency of sequential circuit test generation.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

PASTA: Partial Scan to Enhance Test Compaction.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

On avoiding undetectable faults during test generation.
Proceedings of the 4th European Test Workshop, 1999

Full Scan Fault Coverage With Partial Scan.
Proceedings of the 1999 Design, 1999

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences.
Proceedings of the 36th Conference on Design Automation, 1999

Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction.
Proceedings of the 36th Conference on Design Automation, 1999

Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Vector-Based Functional Fault Models for Delay Faults.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
On methods to match a test pattern generator to a circuit-under-test.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Functional test generation for delay faults in combinational circuits.
ACM Trans. Design Autom. Electr. Syst., 1998

Test sequences to achieve high defect coverage for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Design-for-testability for path delay faults in large combinational circuits using test points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Techniques for minimizing power dissipation in scan and combinational circuits during test application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning.
IEEE Trans. Computers, 1998

Delay fault models for VLSI circuits1.
Integr., 1998

Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits.
Int. J. Found. Comput. Sci., 1998

Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On Synchronizing Sequences and Test Sequence Partitioning.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On Removing Redundant Faults in Synchronous Sequential Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On Test Compaction Objectives for Combinational and Sequential Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

MIX: A Test Generation System for Synchronous Sequential Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Improved built-in test pattern generators based on comparison units for synchronous sequential circuits.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

On finding undetectable and redundant faults in synchronous sequential circuits.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

A Generalized Test Generation Procedure for Path Delay Faults.
Proceedings of the Digest of Papers: FTCS-28, 1998

Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.
Proceedings of the 1998 Design, 1998

A Synthesis Procedure for Flexible Logic Functions.
Proceedings of the 1998 Design, 1998

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration.
Proceedings of the 1998 Design, 1998

Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits .
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Compact test sets for high defect coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On the fault coverage of gate delay fault detecting tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On error correction in macro-based circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

LOCSTEP: a logic-simulation-based test generation procedure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Test Generation for Multiple State-Table Faults in Finite-State Machines.
IEEE Trans. Computers, 1997

On Dictionary-Based Fault Location in Digital Logic Circuits.
IEEE Trans. Computers, 1997

Perspectives on high performance network computing.
Future Gener. Comput. Syst., 1997

On n-detection test sequences for synchronous sequential circuits343.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On Full Reset as a Design-For-Testability Technique.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

On the Detection of Reset Faults in Synchronous Sequential Circuits.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

(Quasi-) Linear Path Delay Fault Tests for Adders.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Built-in test generation for synchronous sequential circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

On Generating Test Sets that Remain Valid in the Presence of Undetected Faults.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation.
Proceedings of the Digest of Papers: FTCS-27, 1997

On the use of reset to increase the testability of interconnected finite-state machines.
Proceedings of the European Design and Test Conference, 1997

On improving genetic optimization based test generation.
Proceedings of the European Design and Test Conference, 1997

Fault Simulation under the Multiple Observation Time Approach using Backward Implications.
Proceedings of the 34st Conference on Design Automation, 1997

TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On the Compaction of Test Sets Produced by Genetic Optimization.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
On the effectiveness of residue code checking for parallel two's complement multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 1996

A novel framework for logic verification in a synthesis environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.
IEEE Trans. Computers, 1996

On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences.
IEEE Trans. Computers, 1996

On the effects of test compaction on defect coverage.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Delay Fault Testing: How Robust are Our Models?
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Local Transformations and Robust Dependent Path Delay.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Fault Location Based on Circuit Partitioning.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Perspectives for High Performance Computing in Workstation Networks.
Proceedings of the High-Performance Computing and Networking, 1996

On Double Transition Faults as a Delay Fault Model.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques.
Proceedings of the Digest of Papers: FTCS-26, 1996

On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem.
Proceedings of the 1996 European Design and Test Conference, 1996

A Fast Optimal Robust Path Delay Fault Testable Adder.
Proceedings of the 1996 European Design and Test Conference, 1996

On Static Compaction of Test Sequences for Synchronous Sequential Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

Minimal Delay Test Sets for Unate Gate Networks.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

"Challenges in Testing".
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
NEST: a nonenumerative test generation method for path delay faults in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

On correction of multiple design errors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing.
IEEE Trans. Computers, 1995

On Fault Simulation for Synchronous Sequential Circuits.
IEEE Trans. Computers, 1995

Aliasing Computation Using Fault Simulation with Fault Dropping.
IEEE Trans. Computers, 1995

Efficient multiple path propagating tests for delay faults.
J. Electron. Test., 1995

Compact test generation for bridging faults under I<sub>DDQ</sub> testing.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Correcting Unidirectional Errors with Nonpositive Hopfield Networks.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Testing-what's missing? An incomplete list of challenges.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

On generating compact test sequences for synchronous sequential circuits.
Proceedings of the Proceedings EURO-DAC'95, 1995

Fast Identification of Robust Dependent Path Delay Faults.
Proceedings of the 32st Conference on Design Automation, 1995

On Synthesis-for-Testability of Combinational Logic Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Static compaction for two-pattern test sets.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
On determining symmetries in inputs of logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

On achieving complete fault coverage for sequential machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation.
IEEE Trans. Computers, 1994

Application of Homing Sequences to Synchronous Sequential Circuit Testing.
IEEE Trans. Computers, 1994

Deleting Vertices to Bound Path Length.
IEEE Trans. Computers, 1994

On identifying undetectable and redundant faults in synchronous sequential circuits.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

On compacting test sets by addition and removal of test vectors.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A Hierarchical Environment for Interactive Test Engineering.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

On testing delay faults in macro-based combinational circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times.
Proceedings of the Digest of Papers: FTCS/24, 1994

On Codeword Testing of Two-Rail and Parity TSC Checkers.
Proceedings of the Digest of Papers: FTCS/24, 1994

On Improving Fault Diagnosis for Synchronous Sequential Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points.
Proceedings of the 31st Conference on Design Automation, 1994

1993
COMPACTEST: a method to generate compact test sets for combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Testing of Fault-Tolerant Hardware Through Partial Control of Inputs.
IEEE Trans. Computers, 1993

Classification of Faults in Synchronous Sequential Circuits.
IEEE Trans. Computers, 1993

Genetic Beam Search for Gate Matrix Layout.
Proceedings of the Sixth International Conference on VLSI Design, 1993

On Unified Delay Fault Testing.
Proceedings of the Sixth International Conference on VLSI Design, 1993

On the Generation of Weights for Weighted Pseudo Random Testing.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

On diagnosis and correction of design errors.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Test generation for path delay faults based on learning.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Theory and Practice of Sequential Machine Testing and Testability.
Proceedings of the Digest of Papers: FTCS-23, 1993

Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity.
Proceedings of the Digest of Papers: FTCS-23, 1993

EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits.
Proceedings of the Digest of Papers: FTCS-23, 1993

A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis.
Proceedings of the European Design Automation Conference 1993, 1993

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

<i>INCREDYBLE-TG</i>: INCREmental DYnamic test generation based on LEarning.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Guaranteed convergence in a class of Hopfield networks.
IEEE Trans. Neural Networks, 1992

The Multiple Observation Time Test Strategy.
IEEE Trans. Computers, 1992

On the design of random pattern testable PLA based on weighted random pattern testing.
J. Electron. Test., 1992

Generalization of independent faults for transition faults.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set.
Proceedings of the Fifth International Conference on VLSI Design, 1992

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

An efficient non-enumerative method to estimate path delay fault coverage.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

On the generation of small dictionaries for fault location.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits.
Proceedings of the Digest of Papers: FTCS-22, 1992

Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.
Proceedings of the Digest of Papers: FTCS-22, 1992

SPADES: a simulator for path delay faults in sequential circuits.
Proceedings of the conference on European design automation, 1992

At-Speed Delay Testing of Synchronous Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1991
Design of robustly testable combinational logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

On Multiple Path Propagating Tests for Path Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Achieving Complete Delay Fault Testability by Extra Inputs.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Testing of Fault-Tolerant Hardware.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Test Generation for Synchronous Sequential Circuits Based on Fault Extraction.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A New Test Generation Method for Sequential Circuits.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model.
Proceedings of the 28th Design Automation Conference, 1991

1990
Long and short covering edges in combination logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

On Symmetric Error Correcting and All Unidirectional Error Detecting Codes.
IEEE Trans. Computers, 1990

Robust tests for parity trees.
J. Electron. Test., 1990

Embedded Totally Self-Checking Checkers: A Practical Design.
IEEE Des. Test Comput., 1990

On Determining Scan Flip-Flops in Partial-Scan Designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

On the design of path delay fault testable combinational circuits.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

Zero aliasing compression.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

On the fault coverage of delay fault detecting tests.
Proceedings of the European Design Automation Conference, 1990

1989
On path selection in combinational logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement.
IEEE Trans. Computers, 1989

A test generation system for path delay faults.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Design of TSC checkers for implementation in CMOS technology.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

On the computation of the ranges of detected delay fault sizes.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

On the Repair of Redundant RAMs.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
A Data Compression Technique for Built-In Self-Test.
IEEE Trans. Computers, 1988

On Self-Fault Diagnosis of the Distributed Systems.
IEEE Trans. Computers, 1988

On the Design of Pseudoexhaustive Testable PLA's.
IEEE Trans. Computers, 1988

On the Detection of Delay Faults.
Proceedings of the Proceedings International Test Conference 1988, 1988

On the design of robust multiple fault testable CMOS combinational logic circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

On the design of robust testable CMOS combinational logic circuits.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987
On Delay Fault Testing in Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A New Approach to the Design of Testable PLA's.
IEEE Trans. Computers, 1987

Distributed Fault-Tolerance of Tree Structures.
IEEE Trans. Computers, 1987

Scan Design Using Standard Flip-Flops.
IEEE Des. Test, 1987

Augmented Shuffle-Exchange Multistage Interconnection Networks.
Computer, 1987

A Parallel PLA Minimization Program.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits.
IEEE Trans. Computers, 1986

Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops.
IEEE Des. Test, 1986

Fault-Tolerance Considerations in Large Multiple-Processor Systems.
Computer, 1986

On the Design of Random Pattern Testable PLAs.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
On the Design of Testable Domino PLAs.
Proceedings of the Proceedings International Test Conference 1985, 1985

Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

On Multipath Multistage Interconnection Networks.
Proceedings of the 5th International Conference on Distributed Computing Systems, 1985

Transistor level test generation for MOS circuits.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984
A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair.
IEEE Trans. Computers, 1984

On CMOS Totally Self-Checking Circuits.
Proceedings of the Proceedings International Test Conference 1984, 1984

A Class of Graphs for Fault-Tolerant Processor Interconnections.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984

A gate level model for CMOS combinational logic circuits with application to fault detection.
Proceedings of the 21st Design Automation Conference, 1984

1983
On Testable Design for CMOS Logic Circuits.
Proceedings of the Proceedings International Test Conference 1983, 1983

A Class of Graphs for Processor Interconnection.
Proceedings of the International Conference on Parallel Processing, 1983

1982
A Fault-Tolerant Communication Architecture for Distributed Systems.
IEEE Trans. Computers, 1982

Design of Easily Testable Microprocessors : A Case Study.
Proceedings of the Proceedings International Test Conference 1982, 1982

1981
A March Test for Functional Faults in Semiconductor Random Access Memories.
IEEE Trans. Computers, 1981

A Testable Design of Iterative Logic Arrays.
IEEE Trans. Computers, 1981

1980
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories.
IEEE Trans. Computers, 1980

Distributed Fault-Tolerance For Large Multiprocessor Systems.
Proceedings of the 7th Annual Symposium on Computer Architecture, 1980

1978
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems.
IEEE Trans. Computers, 1978

On the Detection of Terminal Stuck-Faults.
IEEE Trans. Computers, 1978

A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines.
IEEE Trans. Computers, 1978

1977
Comments on "Minimal Fault Tests for Combinational Networks".
IEEE Trans. Computers, 1977

A Note on Testing Logic Circuits by Transition Counting.
IEEE Trans. Computers, 1977

On Totally Self-Checking Checkers for Separable Codes.
IEEE Trans. Computers, 1977

1976
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes.
IEEE Trans. Computers, 1976

1975
A Routing Algorithm for Computer Communication Networks.
IEEE Trans. Commun., 1975

Fault Detecting Test Sets for Reed-Muller Canonic Networks.
IEEE Trans. Computers, 1975

1974
Further results on decoders for Q -ary output channels (Corresp.).
IEEE Trans. Inf. Theory, 1974

Easily Testable Two-Dimensional Cellular Logic Arrays.
IEEE Trans. Computers, 1974

On Minimally Testable Logic Networks.
IEEE Trans. Computers, 1974

Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions.
IEEE Trans. Computers, 1974

Note on Self-Checking Checkers.
IEEE Trans. Computers, 1974

Design of Two-Level Fault-Tolerant Networks.
IEEE Trans. Computers, 1974

Authors' Reply.
IEEE Trans. Computers, 1974

On the Design of Logic Networks with Redundancy and Testability Considerations.
IEEE Trans. Computers, 1974

1973
A (48, 31, 8) linear code (Corresp.).
IEEE Trans. Inf. Theory, 1973

Complete Test Sets for Logic Functions.
IEEE Trans. Computers, 1973

Fault-Tolerant Asynchronous Networks.
IEEE Trans. Computers, 1973

1972
Forward-Error Correction with Decision Feedback
Inf. Control., September, 1972

New binary codes.
IEEE Trans. Inf. Theory, 1972

Hybrid block- self-orthogonal convolutional codes.
IEEE Trans. Inf. Theory, 1972

Random error and burst correction by iterated codes.
IEEE Trans. Inf. Theory, 1972

On block codes with specified maximum distance (Corresp.).
IEEE Trans. Inf. Theory, 1972

A Design Procedure for Fault-Locatable Switching Circuits.
IEEE Trans. Computers, 1972

Easily Testable Realizations ror Logic Functions.
IEEE Trans. Computers, 1972

Error-Control Techniques for Logic Processors.
IEEE Trans. Computers, 1972

Multiple Fault Detection in Combinational Networks.
IEEE Trans. Computers, 1972

Multiple Faults in Reed-Muller Canonic Networks
Proceedings of the 13th Annual Symposium on Switching and Automata Theory, 1972

1971
Linear Convolutional Codes for Compound Channels
Inf. Control., December, 1971

1970
A Class of High-Rate Double-Error-Correcting Convolutional Codes
Inf. Control., May, 1970

On decoding iterated codes.
IEEE Trans. Inf. Theory, 1970

Circulant bases for cyclic codes (Corresp.).
IEEE Trans. Inf. Theory, 1970

1969
A note on decoding of block codes (Corresp.).
IEEE Trans. Inf. Theory, 1969

A feedback decoding scheme for linear convolutional codes (Corresp.).
IEEE Trans. Inf. Theory, 1969

1968
A Decoding Algorithm for Some Convolutional Codes Constructed from Block Codes
Inf. Control., November, 1968

Further Results on Convolutional Codes Derived from Block Codes
Inf. Control., October, 1968

A Construction for Convolutional Codes Using Block Codes
Inf. Control., January, 1968


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