Chien-Ping Kuo

According to our database, Chien-Ping Kuo authored at least 3 papers between 2021 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2022

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.

Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process.

Chua-Chin Wang, Chien-Ping Kuo

IEEE Trans. Circuits Syst. II Express Briefs, 2021

67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process.

Chua-Chin Wang, Chien-Ping Kuo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021