Ralph Gerard B. Sangalang
Orcid: 0000-0002-4120-382X
According to our database1,
Ralph Gerard B. Sangalang
authored at least 13 papers
between 2021 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.
Integr., May, 2023
Circuits Syst. Signal Process., April, 2023
IET Circuits Devices Syst., March, 2023
Developing an LTE Learning Material: Experiences from a University in a Developing Country.
Proceedings of the International Conference on Information Technology, 2023
FPGA-Based Radio Transceiver Using the TV White Space for Disaster Response Operation.
Proceedings of the International Conference on Information Technology, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process.
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS.
Microelectron. J., 2021