Chua-Chin Wang

Shao-Wei Lu

Wei-Chih Chang

Integr., May, 2023

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder.

[BibT_eX]

[DOI]

Wen-Shou Yang

Circuits Syst. Signal Process., April, 2023

A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process.

[BibT_eX]

[DOI]

I-Ting Tseng

Yi-Jen Chiu

Yu-Cheng Lin

IET Circuits Devices Syst., March, 2023

A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

SiC MOSFET High Side Gate Driver Design Using HV CMOS Process.

[BibT_eX]

[DOI]

Jui-Min Kuo

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process.

[BibT_eX]

[DOI]

Shih-Heng Luo

Proceedings of the International Conference on IC Design and Technology, 2023

Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS.

[BibT_eX]

[DOI]

You-Wei Shen

Shiva Reddy

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Lightweight Deep Neural Network for Joint Learning of Underwater Object Detection and Color Conversion.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2022

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture.

[BibT_eX]

[DOI]

Li Lin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process.

[BibT_eX]

[DOI]

Shiva Reddy

Proceedings of the International Conference on IC Design and Technology, 2022

Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique.

[BibT_eX]

[DOI]

Bo-Hao Liao

Durga Srikanth Kamarajugadda

Proceedings of the International Conference on IC Design and Technology, 2022

A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic.

[BibT_eX]

[DOI]

Lung-Jieh Yang

Balasubramanian Esakki

Sivaperumal Sampath

Proceedings of the International Conference on IC Design and Technology, 2022

A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology.

[BibT_eX]

[DOI]

Jyoshnavi Akiri

Lung-Jieh Yang

Balasubramanian Esakki

Sivaperumal Sampath

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM.

[BibT_eX]

[DOI]

Chia-Yi Huang

Chia-Hung Yeh

IEEE Trans. Very Large Scale Integr. Syst., 2021

A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit.

[BibT_eX]

[DOI]

I-Ting Tseng

IEEE Trans. Circuits Syst. II Express Briefs, 2021

200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process.

[BibT_eX]

[DOI]

Chien-Ping Kuo

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

0.7 % error rate 3A bidirectional current sensor using high voltage CMOS process.

[BibT_eX]

[DOI]

Microelectron. J., 2021

An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS.

[BibT_eX]

[DOI]

Po-Kai Su

Jessica Velasco

Microelectron. J., 2021

High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2021

2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2021

Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer.

[BibT_eX]

[DOI]

Yung-Yuan Ho

Proceedings of the 18th International SoC Design Conference, 2021

On-chip CMOS Corner Detector Design for Panel Drivers.

[BibT_eX]

[DOI]

Ying-Xuan Chen

Proceedings of the 18th International SoC Design Conference, 2021

67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process.

[BibT_eX]

[DOI]

Chien-Ping Kuo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction.

[BibT_eX]

[DOI]

Uday Kiran Naidu Ekkurthi

Chia-Yi Huang

Chia-Hung Yeh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop.

[BibT_eX]

[DOI]

Venkatesh Dasari

Jyoshnavi Akiri

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology.

[BibT_eX]

[DOI]

Wen-Shou Yang

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment.

[BibT_eX]

[DOI]

Wen-Jian Su

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Power-effective ROM-less DDFS Design Approach with High SFDR Performance.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique.

[BibT_eX]

[DOI]

Ssu-Wei Huang

IEEE Trans. Circuits Syst., 2020

A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2020

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2020

100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*.

[BibT_eX]

[DOI]

Shao-Wei Lu

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

3D-Modeling Dataset Augmentation for Underwater AUV Real-time Manipulations.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019

74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2019

A 1.5A 88.6% Li-ion Battery Charger Design using Pulse Swallow Technique in Light Load.

[BibT_eX]

[DOI]

Guan-Xian Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM.

[BibT_eX]

[DOI]

Chia-Hsin Hsu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Ultra Low Power Single-ended 6T SRAM Using 40 nm CMOS Technology.

[BibT_eX]

[DOI]

I-Ting Tseng

Proceedings of the International Conference on IC Design and Technology, 2019

A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2019

A Low Frequency OTA Design with Temperature-Insensitive Variable Transconductance Using 180-nm CMOS Technology.

[BibT_eX]

[DOI]

Nanang Sulistiyanto

Robert Rieger

Proceedings of the International Conference on IC Design and Technology, 2019

A Broken Line Detection Circuit for Multi-cell Li-ion Battery Module1.

[BibT_eX]

[DOI]

Chien-Hua Chu

Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A High-Precision CMOS Temperature Sensor with Thermistor Linear Calibration in the (-5 °C, 120 °C) Temperature Range.

[BibT_eX]

[DOI]

Jhih-Cheng You

Sensors, 2018

A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2018

A frequency-shift readout system with offset cancellation OPA for portable devices of marijuana detection.

[BibT_eX]

[DOI]

Hao-Chun Huang

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate.

[BibT_eX]

[DOI]

Ssu-Wei Huang

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation.

[BibT_eX]

[DOI]

Kai-Wei Ruan

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine.

[BibT_eX]

[DOI]

Sensors, 2017

A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM.

[BibT_eX]

[DOI]

Yu-Hsun Su

Microelectron. J., 2017

A 19.38 dBm OIP3 gm-boosted up-conversion CMOS mixer for 5-6 GHz application.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Dynamic power estimation for ROM-less DDFS designs using switching activity analysis.

[BibT_eX]

[DOI]

Wei Wang

Yuan-Yuan Xu

Proceedings of the International SoC Design Conference, 2017

A pipeline ROM-less DDFS using equal-division interpolation.

[BibT_eX]

[DOI]

Hsiang-Yu Shih

Proceedings of the International SoC Design Conference, 2017

A primary-side output current estimator with process compensator for flyback LED drivers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

State of charge, state of health, and state of function monitoring for EV BMS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2017

High-voltage bidirectional current sensor.

[BibT_eX]

[DOI]

Hsiu-Chun Tsai

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

A Leakage Compensation Design for Low Supply Voltage SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

High-voltage on-chip current sensor design and analysis for battery modules.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2016

A novel frequency-shift readout system for CEA concentration detection application.

[BibT_eX]

[DOI]

Yun-Shen Liu

Proceedings of the International SoC Design Conference, 2016

Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process.

[BibT_eX]

[DOI]

Chia-Lung Hsieh

Proceedings of the International SoC Design Conference, 2016

An accurate phase shift detector using bulk voltage boosting technique for sensing applications.

[BibT_eX]

[DOI]

Yu-Ting Tu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A nano-scale 2×VDD I/O buffer with encoded PV compensation technique.

[BibT_eX]

[DOI]

Yu-Lin Teng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above.

[BibT_eX]

[DOI]

Yan-You Chou

Proceedings of the International Conference on IC Design and Technology, 2016

On-chip accurate primary-side output current estimator for flyback LED driver control.

[BibT_eX]

[DOI]

Teng-Wei Huang

Proceedings of the International Conference on IC Design and Technology, 2016

A flyback driver with adaptive switching frequency control for smart lighting1.

[BibT_eX]

[DOI]

Teng-Wei Huang

Proceedings of the IEEE International Conference on Consumer Electronics, 2016

2015

A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A ±3.07% frequency variation clock generator implemented using HV CMOS process.

[BibT_eX]

[DOI]

Microelectron. J., 2015

A 30 V rail-to-rail operational amplifier.

[BibT_eX]

[DOI]

Microelectron. J., 2015

Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring.

[BibT_eX]

[DOI]

Tzu-Chao Wu

Microelectron. J., 2015

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology.

[BibT_eX]

[DOI]

Microelectron. J., 2015

A wide range and high conversion gain power detector for frequency shift sensing applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology.

[BibT_eX]

[DOI]

Wei Lin

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

A high-voltage Transceiver for electrical vehicle Battery Management Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2015

10 Mbps high-voltage digital transciever on single die for 50 V voltage swing.

[BibT_eX]

[DOI]

Min-Yu Tseng

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2014

Noninvasive Control of the Power Transferred to an Implanted Device by an Ultrasonic Transcutaneous Energy Transfer Link.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Eng., 2014

A CMOS wide-range temperature sensor with process compensation and second-order calibration for Battery Management Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process.

[BibT_eX]

[DOI]

Chiang-Hsiang Liao

Sih-Yu Chen

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An on-chip high-voltage current sensor for battery module monitoring.

[BibT_eX]

[DOI]

Sheng-Syong Wang

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation.

[BibT_eX]

[DOI]

Kai-Wei Ruan

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

A 20 GHz power detector with 176 mV/dB conversion gain.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

An all-digital battery capacity monitor using calibrated current estimation approach.

[BibT_eX]

[DOI]

Min-Yu Tseng

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Protein Concentration Measurement System Using a Flexural Plate-Wave Frequency-Shift Readout Technique.

[BibT_eX]

[DOI]

Sensors, 2013

A 2×VDD output buffer with PVT detector for slew rate compensation.

[BibT_eX]

[DOI]

Microelectron. J., 2013

A low-power transceiver design for FlexRay-based communication systems.

[BibT_eX]

[DOI]

Microelectron. J., 2013

A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology.

[BibT_eX]

[DOI]

Hsin-Yuan Tseng

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High voltage operational amplifier and high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

A delay-based transceiver with over-current protection for ECU nodes in automobile FlexRay systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2012

A Signed Array Multiplier with Bypassing Logic.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

A Single-Chip 60-V Bulk Charger for Series Li-Ion Batteries With Smooth Charge-Mode Transition.

[BibT_eX]

[DOI]

Jen-Wei Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers.

[BibT_eX]

[DOI]

Microelectron. J., 2012

Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector.

[BibT_eX]

[DOI]

Microelectron. J., 2012

A slew rate self-adjusting 2×VDD output buffer With PVT compensation.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Feed-forward Output Swing Prediction AGC with Parallel-Detect Singular-Store Peak Detector.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A fast FPW-based protein concentration measurement system.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A digital over-temperature protector for FlexRay systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Temperature and process compensated clock generator using feedback TPC bias.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process.

[BibT_eX]

[DOI]

Sih-Yu Chen

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

A high voltage analog multiplexer with digital calibration for battery management systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Configurable Active Star design for automobile FlexRay systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

A PLC transceiver design of in-vehicle power line in FlexRay-based automotive communication systems.

[BibT_eX]

[DOI]

Chun-Ming Huang

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

A fast FPW allergy analyzer prototype for point of care (POC).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

A reconfigurable 16-channel HV stimulator ASIC for Spinal Cord Stimulation systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Linear programmable gain amplifier using reconfiguration local-feedback transconductors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

One-Time-Implantable Spinal Cord Stimulation System Prototype.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2011

A high precision low dropout regulator with nested feedback loops.

[BibT_eX]

[DOI]

Ron-Chi Kuo

Tung-Han Tsai

Microelectron. J., 2011

A high-efficiency DC-DC buck converter for sub-2×VDD power supply.

[BibT_eX]

[DOI]

Microelectron. J., 2011

A 48-dB dynamic gain range/stage linear-in-dB low power Variable Gain Amplifier for direct-conversion receivers.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

A high voltage battery charger with smooth charge mode transition in BCD process.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Energy-Efficient Double-Edge Triggered Flip-Flop.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2010

A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Guest Editorial Special Issue on ISCAS 2009.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage.

[BibT_eX]

[DOI]

Ron-Chi Kuo

Jen-Wei Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 1/2 times hbox VDD to 3 times hbox VDD Bidirectional I/O Buffer With a Dynamic Gate Bias Generator.

[BibT_eX]

[DOI]

Chia-Hao Hsu

Yi-Cheng Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Self-Disabled Sensing Technique for Content-Addressable Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

All-Digital Frequency Synthesizer Using a Flying Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A low-power 2.45 GHz WPAN modulator/demodulator.

[BibT_eX]

[DOI]

Microelectron. J., 2010

A 125-MHz wide-range mixed-voltage I/O buffer using gated Floating N-well circuit.

[BibT_eX]

[DOI]

Szu-Chia Liao

Yi-Cheng Liu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A mini-invasive multi-function biomedical pressure measurement system ASIC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A high precision low dropout regulator with nested feedback loops.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

A PCI166-compatible 3×VDD-tolerant mixed-voltage I/O buffer.

[BibT_eX]

[DOI]

Ron-Chi Kuo

Hsiao-Han Hou

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Low-Power Multiplier Design Using a Bypassing Technique.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology.

[BibT_eX]

[DOI]

Tieh-Yen Chang

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Baseband Receiver Design for the MBOA Ultra Wideband Wireless Personal Area Networks.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2009

A Drive Circuit for Piezoelectric Devices with Low Harmonics Content.

[BibT_eX]

[DOI]

Shaul Ozeri

Doron Shmilovitz

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.

[BibT_eX]

[DOI]

Pai-Li Liu

J. Signal Process. Syst., 2008

A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators.

[BibT_eX]

[DOI]

VLSI Design, 2008

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

All-MOS ASK Demodulator for Low-Frequency Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Mini-Invasive Long-Term Bladder Urine Pressure Measurement ASIC and System.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2008

A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants.

[BibT_eX]

[DOI]

Microelectron. J., 2008

A low-power ADPLL using feedback DCO quarterly disabled in time domain.

[BibT_eX]

[DOI]

Chi-Chun Huang

Sheng-Lun Tseng

Microelectron. J., 2008

A single-chip CMOS IF-band converter design for DVB-T receivers.

[BibT_eX]

[DOI]

Microelectron. J., 2008

A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2008

A mini-invasive multi-function bladder urine pressure measurement system.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Power-saving nano-scale DRAMs with an adaptive refreshing clock generator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A power-aware 2-dimensional bypassing multiplier using cell-based design flow.

[BibT_eX]

[DOI]

Yan-Jhin Ciou

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 32-bit carry lookahead adder design using complementary all-N-transistor logic.

[BibT_eX]

[DOI]

Chun-Ying Juan

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Mixed-voltage I/O buffer using 0.35 μm CMOS technology.

[BibT_eX]

[DOI]

Wei-Chih Chang

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A self-disable sense technique with differential NAND cell for content-addressable memories.

[BibT_eX]

[DOI]

Chi-Chun Huang

Jun-Han Wu

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation.

[BibT_eX]

[DOI]

Jian-Ming Huang

Chia-Chuan Lee

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A ROM-less DDFS using a nonlinear DAC with an error compensation current array.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A Li-ion battery charging design for biomedical implants.

[BibT_eX]

[DOI]

Chi-Chun Huang

Shou-Fu Yen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme.

[BibT_eX]

[DOI]

Ching-Li Lee

Wun-Ji Lin

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

An 80MHz PLL with 72.7ps peak-to-peak jitter.

[BibT_eX]

[DOI]

Microelectron. J., 2007

Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator.

[BibT_eX]

[DOI]

Microelectron. J., 2007

A Low-power Sensorless Inverter Controller of Brushless DC Motors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

High-sensitivity and high-mobility compact DVB-T receiver for in-car entertainment.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2006

An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A 4-Kb low power 4-T SRAM design with negative word-line gate drive.

[BibT_eX]

[DOI]

Ching-Li Lee

Wun-Ji Lin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 6.57 mW ZigBee transceiver for 868/915 MHz band.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Codec Design for Variable-Length to Fixed-Length Data Conversion for H.263.

[BibT_eX]

[DOI]

Jia-Hao Li

Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006

Engery-Efficient Double-Edge Triggered Flip-Flop Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A temperature-insensitive self-recharging circuitry used in DRAMs.

[BibT_eX]

[DOI]

Yih-Long Tseng

Chih-Chiang Chiu

IEEE Trans. Very Large Scale Integr. Syst., 2005

A multiparameter implantable microstimulator SOC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Low-cost video decoder with 2D2L comb filter for NTSC digital TVs.

[BibT_eX]

[DOI]

Ching-Li Lee

Ming-Kai Chang

IEEE Trans. Consumer Electron., 2005

A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers.

[BibT_eX]

[DOI]

Jian-Ming Huang

Hsian-Chang Cheng

IEEE Trans. Consumer Electron., 2005

Low-Power Small-Area Digital I/O Cell.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

High-PSR bias circuitry for NTSC sync separation.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A phase-adjustable negative phase shifter using a single-shot locking method.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A C-less ASK demodulator for implantable neural interfacing chips.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

An area-saving decoder structure for ROMs.

[BibT_eX]

[DOI]

Ya-Hsin Hsueh

IEEE Trans. Very Large Scale Integr. Syst., 2003

An SRAM design using dual threshold voltage transistors and low-power quenchers.

[BibT_eX]

[DOI]

Kuo-Long Chen

IEEE J. Solid State Circuits, 2003

Dual-polarity high voltage generator design for non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A boosted wordline voltage generator for low-voltage memories.

[BibT_eX]

[DOI]

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002

Improved Design of C2PL 3-2 Compressors for Inner Product Processing.

[BibT_eX]

[DOI]

VLSI Design, 2002

A Fast Dynamic 64-bit Comparator with Small Transistor Count.

[BibT_eX]

[DOI]

VLSI Design, 2002

An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method.

[BibT_eX]

[DOI]

Ya-Hsin Hsueh

Shao-Ku Huang

VLSI Design, 2002

Design of an Inter-plane Circuit for Clocked PLAs.

[BibT_eX]

[DOI]

VLSI Design, 2002

A low-cost plasma display panel data dispatcher for image enhancement.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2002

Image Processing Techniques for Wafer Defect Cluster Identification.

[BibT_eX]

[DOI]

Chi-Feng Wu

IEEE Des. Test Comput., 2002

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.

[BibT_eX]

[DOI]

Hsien-Chih She

Ron Hu

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A ROM-less direct digital frequency synthesizer by using trigonometric quadruple angle formula.

[BibT_eX]

[DOI]

Hsien-Chih She

Ron Hu

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

6-T SRAM using dual threshold voltage transistors and low-power quenchers.

[BibT_eX]

[DOI]

Kuo-Long Chen

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2001

A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems.

[BibT_eX]

[DOI]

Comput. Commun., 2001

A 1.25 GHz 32-bit tree-structured carry lookahead adder.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 1.0 GHz clock generator design with a negative delay using a single-shot locking method.

[BibT_eX]

[DOI]

Yih-Long Tseng

Rong-Sui Kao

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Design of a cycle-efficient 64b/32b integer divider using a table-sharing method.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

An area-saving 3-dimensional decoder structure for ROMs.

[BibT_eX]

[DOI]

Ya-Hsin Hsueh

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs.

[BibT_eX]

[DOI]

Chih-Chiang Chiu

Yu-Tsung Chien

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Design and Analysis of Digital Ratioed Compressors for Inner Product Processing.

[BibT_eX]

[DOI]

VLSI Design, 2000

Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library.

[BibT_eX]

[DOI]

I-Yen Chang

VLSI Design, 2000

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop.

[BibT_eX]

[DOI]

VLSI Design, 2000

A deterministic capacity-finding method for multi-valued exponential BAM.

[BibT_eX]

[DOI]

Shiou-Ming Hwang

IEEE Trans. Syst. Man Cybern. Part A, 2000

Single-ended SRAM with high test coverage and short test time.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

Fuzzy data processing using polynomial bidirectional hetero-associative network.

[BibT_eX]

[DOI]

Inf. Sci., 2000

A fast dynamic 64-bit comparator with small transistor count.

[BibT_eX]

[DOI]

Hsin-Long Wu

Chih-Feng Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Improved design of C2PL 3-2 compressors with less transistor count.

[BibT_eX]

[DOI]

Chenn-Jung Hunng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Design of an inter-plane circuit for clocked PLAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Novel Neural Architecture with High Storage Capacity.

[BibT_eX]

[DOI]

Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1999

Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Data compression by the recursive algorithm of exponential bidirectional associative memory.

[BibT_eX]

[DOI]

Chang-Rong Tsai

IEEE Trans. Syst. Man Cybern. Part B, 1998

The Majority Theorem of Centralized Multiple BAMs Networks.

[BibT_eX]

[DOI]

Inf. Sci., 1998

Fuzzy data recall using polynomial bidirectional hetero-correlator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

1997

Digital Design of Discrete Exponential Bidirectional Associative Memory.

[BibT_eX]

[DOI]

Chih-Lwan Fan

J. VLSI Signal Process., 1997

1996

Capacity analysis of the asymptotically stable multi-valued exponential bidirectional associative memory.

[BibT_eX]

[DOI]

Shiou-Ming Hwang

Jyh-Ping Lee

IEEE Trans. Syst. Man Cybern. Part B, 1996

Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 1996

1995

The decision-making properties of discrete multiple exponential bidirectional associative memories.

[BibT_eX]

[DOI]

Jyh-Ping Lee

IEEE Trans. Neural Networks, 1995

An analysis of high-capacity discrete exponential BAM.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1995

Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory.

[BibT_eX]

[DOI]

Jeng-Ming Wu

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Realization of bidirectional associative memory using a pseudo-parallel searching approach.

[BibT_eX]

[DOI]

In-Hau Horng

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994

A robust continuous model for evidential reasoning.

[BibT_eX]

[DOI]

J. Intell. Robotic Syst., 1994

A Modified Measure for Fuzzy Subsethood.

[BibT_eX]

[DOI]

Inf. Sci., 1994

A Polar Model for Evidential Reasoning.

[BibT_eX]

[DOI]