Chihiro Yoshimura
Orcid: 0000-0001-8822-9595
According to our database1,
Chihiro Yoshimura
authored at least 20 papers
between 2013 and 2024.
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Bibliography
2024
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale.
CoRR, 2024
2023
Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference.
Proceedings of the Active Inference - 4th International Workshop, 2023
Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers.
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023
2022
Extended-Self Recognition for Autonomous Agent Based on Controllability and Predictability.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2022
2021
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2020
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2017
Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing.
Int. J. Netw. Comput., 2017
2016
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing.
IEEE J. Solid State Circuits, 2016
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution.
Int. J. Netw. Comput., 2016
Assessing bluegill (Lepomis macrochirus) habitat suitability using partial dependence function combined with classification approaches.
Ecol. Informatics, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution.
Proceedings of the Third International Symposium on Computing and Networking, 2015
2013
Spatial computing architecture using randomness of memory cell stability under voltage control.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013