Hiroyuki Mizuno
Orcid: 0000-0002-1213-9021
According to our database1,
Hiroyuki Mizuno
authored at least 34 papers
between 1996 and 2024.
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Bibliography
2024
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale.
CoRR, 2024
CoRR, 2024
2023
IET Cyper-Phys. Syst.: Theory & Appl., March, 2023
Mixbiotic society measures: Comparison of organizational structures based on communication simulation.
CoRR, 2023
CoRR, 2023
The impact of individual information exchange strategies on the distribution of social wealth.
CoRR, 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference.
Proceedings of the Active Inference - 4th International Workshop, 2023
Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers.
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023
2022
Extended-Self Recognition for Autonomous Agent Based on Controllability and Predictability.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2022
2021
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021
2016
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing.
IEEE J. Solid State Circuits, 2016
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution.
Int. J. Netw. Comput., 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution.
Proceedings of the Third International Symposium on Computing and Networking, 2015
2014
Proceedings of the American Control Conference, 2014
2013
Spatial computing architecture using randomness of memory cell stability under voltage control.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
Proceedings of the ICPP 2009, 2009
2008
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits, 2007
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution.
IEEE J. Solid State Circuits, 2007
2006
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Hierarchical power distribution and power management scheme for a single chip mobile processor.
Proceedings of the 43rd Design Automation Conference, 2006
2001
Low-Voltage Embedded-RAM Technology: Present and Future.
Proceedings of the SOC Design Methodologies, 2001
1999
A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio.
IEEE Trans. Very Large Scale Integr. Syst., 1999
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode.
IEEE J. Solid State Circuits, 1999
On the Use of Density Distribution of Keywords for Automated Generation of Hypertext Links from Arbitrary Parts of Documents.
Proceedings of the Fifth International Conference on Document Analysis and Recognition, 1999
1998
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1997
IEEE J. Solid State Circuits, 1997
1996
IEEE J. Solid State Circuits, 1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996