Masanao Yamaoka
Orcid: 0000-0001-8677-125X
According to our database1,
Masanao Yamaoka
authored at least 40 papers
between 2002 and 2021.
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Bibliography
2021
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes.
Soft Comput., 2021
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.
IEEE J. Solid State Circuits, 2021
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2020
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines.
IEICE Trans. Inf. Syst., 2019
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity.
Proceedings of the Theory and Practice of Natural Computing - 7th International Conference, 2018
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
2017
Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing.
Int. J. Netw. Comput., 2017
An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
2016
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing.
IEEE J. Solid State Circuits, 2016
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution.
Int. J. Netw. Comput., 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
2015
Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution?
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution.
Proceedings of the Third International Symposium on Computing and Networking, 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Spatial computing architecture using randomness of memory cell stability under voltage control.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2010
2009
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis.
Proceedings of the ESSCIRC 2008, 2008
2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors.
IEEE J. Solid State Circuits, 2006
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
2005
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor.
IEEE J. Solid State Circuits, 2005
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Trans. Electron., 2005
2004
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme.
IEEE J. Solid State Circuits, 2004
2002
A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit.
IEEE J. Solid State Circuits, 2002