Chin Hau Hoo

According to our database, Chin Hau Hoo authored at least 7 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling.

Chin Hau Hoo, Akash Kumar

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding.

Chin Hau Hoo, Akash Kumar

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning.

Chin Hau Hoo, Yajun Ha, Akash Kumar

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

ParaLaR: A parallel FPGA router based on Lagrangian relaxation.

Chin Hau Hoo, Akash Kumar, Yajun Ha

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2013

Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology.

Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm.

Chin Hau Hoo, Yajun Ha, Akash Kumar

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay.

Chin Hau Hoo, Akash Kumar

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012