Kaushik De

According to our database1, Kaushik De authored at least 22 papers between 1989 and 2018.

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Bibliography

2018
Modeling Impact of Execution Strategies on Resource Utilization.
Proceedings of the 14th IEEE International Conference on e-Science, 2018

Fine-Grained Processing Towards HL-LHC Computing in ATLAS.
Proceedings of the 14th IEEE International Conference on e-Science, 2018

2017
High-Throughput Computing on High-Performance Platforms: A Case Study.
Proceedings of the 13th IEEE International Conference on e-Science, 2017

2015
Unified System for Processing Real and Simulated Data in the ATLAS Experiment.
Proceedings of the Selected Papers of the XVII International Conference on Data Analytics and Management in Data Intensive Domains (DAMDID/RCDL 2015), 2015

2012
Abstract: PanDA: Next Generation Workload Management and Analysis System for Big Data.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Poster: PanDA: Next Generation Workload Management and Analysis System for Big Data.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

2008
ViGs: A grid simulation and monitoring tool for ATLAS workflows.
Proceedings of the 2008 Workshop on Many-Task Computing on Grids and Supercomputers, 2008

2007
Hardware accelerated constrained random test generation.
IET Computers & Digital Techniques, 2007

2004
The Grid2003 Production Grid: Principles and Practice.
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Proceedings of the 13th International Symposium on High-Performance Distributed Computing (HPDC-13 2004), 2004

Accurate pre-layout estimation of standard cell characteristics.
Proceedings of the 41th Design Automation Conference, 2004

2000
Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

1997
Test methodology for embedded cores which protects intellectual property.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1995
Failure Analysis for Full-Scan Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Parallel algorithms for logic synthesis using the MIS approach.
Proceedings of IPPS '95, 1995

1994
RSYN: a system for automated synthesis of reliable multilevel circuits.
IEEE Trans. VLSI Syst., 1994

A portable parallel algorithm for logic synthesis using transduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Parallel Logic Synthesis Using Partitioning.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
PREST: a system for logic partitioning and resynthesis for testability.
IEEE Trans. VLSI Syst., 1993

A Shared Memory Parallel Algorithm for Logic Synthesis.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
ProperSYN: a portable parallel algorithm for logic synthesis.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Logic Partitioning and Resynthesis for Testability.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1989
Synthesis of delay fault testable combinational logic.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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