Chuan-Kang Liang

According to our database1, Chuan-Kang Liang authored at least 2 papers between 2006 and 2008.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2006
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit.
IEEE J. Solid State Circuits, 2006


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