Rong-Jyi Yang

According to our database, Rong-Jyi Yang authored at least 13 papers between 2004 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM.

Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.

Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang

IEEE Trans. Very Large Scale Integr. Syst., 2015

2012

A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm.

Wei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, Chao-Chyun Chen

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

2008

An All-Digital Fast-Locking Programmable DLL-Based Clock Generator.

Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition.

Chi-Shuang Oulee, Rong-Jyi Yang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology.

Rong-Jyi Yang, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2007

A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm.

Rong-Jyi Yang, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2007

2006

A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit.

Rong-Jyi Yang, Kuan-Hua Chao, Shen-Iuan Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit.

Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2006

2005

A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector.

Rong-Jyi Yang, Shen-Iuan Liu

IEICE Trans. Electron., 2005

A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs.

Rong-Jyi Yang, Shen-Iuan Liu

IEICE Trans. Electron., 2005

2004

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.

Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet.

Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2004