Sy-Chyuan Hwu

According to our database, Sy-Chyuan Hwu authored at least 6 papers between 2006 and 2015.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2015

An RF Receiver for Intra-Band Carrier Aggregation.

Sy-Chyuan Hwu, Behzad Razavi

IEEE J. Solid State Circuits, 2015

2014

A receiver architecture for intra-band carrier aggregation.

Sy-Chyuan Hwu, Behzad Razavi

Proceedings of the Symposium on VLSI Circuits, 2014

2008

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector.

Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2008

2007

A Multi-Band Burst-Mode Clock and Data Recovery Circuit.

Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu

IEICE Trans. Electron., 2007

2006

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit.

Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2006

A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS.

Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006