Chuan-Yung Tsai

According to our database1, Chuan-Yung Tsai authored at least 14 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
FusedProp: Towards Efficient Training of Generative Adversarial Networks.
CoRR, 2020

2016
Tensor Switching Networks.
Proceedings of the Advances in Neural Information Processing Systems 29: Annual Conference on Neural Information Processing Systems 2016, 2016

2015
Measuring and Understanding Sensory Representations within Deep Networks Using a Numerical Optimization Framework.
CoRR, 2015

2012
A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A cortex-like model for rapid object recognition using feature-selective hashing.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

2009
Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices.
IEEE Trans. Circuits Syst. Video Technol., 2009

Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

2008
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder.
J. Signal Process. Syst., 2008

2007
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2007

2006
Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Low power and power aware fractional motion estimation of H.264/AVC for mobile applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

2005
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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