Tzu-Der Chuang

According to our database1, Tzu-Der Chuang authored at least 23 papers between 2007 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
A VVC Proposal With Quaternary Tree Plus Binary-Ternary Tree Coding Block Structure and Advanced Coding Techniques.
IEEE Trans. Circuits Syst. Video Technol., 2020

2016
Intra Block Copy in HEVC Screen Content Coding Extensions.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Palette Mode Coding in HEVC Screen Content Coding Extension.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Improved palette index map coding on HEVC SCC.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
Palette mode - A new coding tool in screen content coding extensions of HEVC.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

Block Vector Prediction for Intra Block Copying in HEVC Screen Content Coding.
Proceedings of the 2015 Data Compression Conference, 2015

2011
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension.
J. Signal Process. Syst., 2010

A 212 MPixels/s 4096 ˟ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications.
IEEE J. Solid State Circuits, 2010

Video encoder design for high-definition 3D video communication systems.
IEEE Commun. Mag., 2010

A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A multimedia semantic analysis SoC (SASoC) with machine-learning engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Low bandwidth decoder framework for H.264/AVC scalable extension.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Mapping Scalable Video Coding decoder on multi-core stream processors.
Proceedings of the 2009 Picture Coding Symposium, 2009

A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A Branch Selection Multi-symbol High throughput CABAC Decoder Architecture for H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control.
Proceedings of the IEEE International Conference on Acoustics, 2009

2008
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Technol., 2008

Frame-parallel design strategy for high definition B-frame H.264/AVC encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 100 MHz 1920×1080 HD-Photo 20 frames/sec JPEG XR encoder design.
Proceedings of the International Conference on Image Processing, 2008

2007
Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007


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