Liang-Gee Chen

According to our database1, Liang-Gee Chen
  • authored at least 343 papers between 1991 and 2018.
  • has a "Dijkstra number"2 of four.

Awards

IEEE Fellow

IEEE Fellow 2001, "For contributions to algorithm and architecture design for video coding systems.".

Timeline

Legend:

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In proceedings 
Article 
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Links

On csauthors.net:

Bibliography

2018
A 473 μW wireless 16-channel neural recording SoC with RF energy harvester.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Simple online and realtime tracking with spherical panoramic camera.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

GPU-accelerated high-resolution image stitching with better initial guess.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017
Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation.
IEEE Trans. Image Processing, 2017

Accurate and fast segment-based cost aggregation algorithm for stereo matching.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

A 120 fps 1080p resolution block-based feature extraction architecture implementation for real-time action recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Interactive sticker system with Intel RealSense.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017

2016
Efficient Hardware Architecture for Large Disparity Range Stereo Matching Based on Belief Propagation.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Accelerated local feature extraction in a reuse scheme for efficient action recognition.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

3-D perception enhancement in autostereoscopic TV by depth cue for 3-D model interaction.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016

2015
A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques.
J. Solid-State Circuits, 2015

23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Memory efficient architecture for belief propagation based disparity estimation.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A real-time 3D interactive system with stereo camera in the uncertain background.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Fast realistic refocusing for sparse light fields.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014
Region-of-unpredictable determination for accelerated full-frame feature generation in video sequences.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Automatic video segmentation and object tracking with real-time RGB-D data.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

A real-time system for object detection and location reminding with RGB-D camera.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Interactive clothing retrieval system.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

On-the-fly fashion photograph recommendation system with robust face shape features.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem.
Proceedings of the IEEE International Conference on Acoustics, 2014

An integrated system for object tracking, detection, and online learning with real-time RGB-D video.
Proceedings of the IEEE International Conference on Acoustics, 2014

2013
Video Compression.
Proceedings of the Handbook of Signal Processing Systems, 2013

Guest Editorial: Special Section on New Software/Hardware Paradigms for Error-Tolerant Multimedia Systems.
IEEE Trans. Multimedia, 2013

Brain-Inspired Framework for Fusion of Multiple Depth Cues.
IEEE Trans. Circuits Syst. Video Techn., 2013

Low-power multi-processor system architecture design for universal biomedical signal processing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Intelligent document capturing and blending system based on robust feature matching with an active camera.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

3D hand localization by low-cost webcams.
Proceedings of the Three-Dimensional Image Processing (3DIP) and Applications 2013, 2013

2012
Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution.
IEEE Trans. VLSI Syst., 2012

A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video.
IEEE Trans. Consumer Electronics, 2012

A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications.
J. Solid-State Circuits, 2012

An intelligent depth-based obstacle detection system for visually-impaired aid applications.
Proceedings of the 13th International Workshop on Image Analysis for Multimedia Interactive Services, 2012

A 69mW 140-meter/60fps and 60-meter/300fps intelligent vision SoC for versatile automotive applications.
Proceedings of the Symposium on VLSI Circuits, 2012

A Chip Architecture for Compressive Sensing Based Detection of IC Trojans.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

WarmL1: A warm-start homotopy-based reconstruction algorithm for sparse signals.
Proceedings of the 2012 IEEE International Symposium on Information Theory, 2012

A high speed feature matching architecture for real-time video stabilization.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

iSense3D: A real-time viewpoint-aware 3D video synthesis system.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012

3D image correction by Hilbert Huang decomposition.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012

Robust moving object tracking and trajectory prediction for visual navigation in dynamic environments.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012

A viewer centric depth adjustment for stereoscopic images.
Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

Compressive Sensing based Client-Cloud system for 3D depth reconstruction.
Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

An intelligent depth-based obstacle detection for mobile applications.
Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

Fast adaptive loop filter algorithm for high efficiency video coding.
Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

A real-time multi-user face unlock system via fast sparse coding approximation.
Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

Accurate positioning system based on street view recognition.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Assessing normality of heart sound by matching pursuit residue with frequency-domain-based templates.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Channel selection for epilepsy seizure prediction method based on machine learning.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

2011
Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation.
Signal Processing Systems, 2011

Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC.
Signal Processing Systems, 2011

Hardware-Efficient Belief Propagation.
IEEE Trans. Circuits Syst. Video Techn., 2011

A real-time 1080p 2D-to-3D video conversion system.
IEEE Trans. Consumer Electronics, 2011

Trends in Design and Implementation of Signal Processing Systems [In the Spotlight].
IEEE Signal Process. Mag., 2011

Perceptual multi-cues 2D-to-3D conversion system.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011

A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A cortex-like model for rapid object recognition using feature-selective hashing.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

Smart display: A mobile self-adaptive projector-camera system.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Six-dimensional free-viewpoint synthesis flow for QFHD free-viewpoint/multiview 3DTV applications.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Algorithm and architecture design of a knowledge-based vehicle tracking for intelligent cruise control.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Algorithm and implementation of multi-channel spike sorting using GPU in a home-care surveillance system.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Design and implementation of cubic spline interpolation for spike sorting microsystems.
Proceedings of the IEEE International Conference on Acoustics, 2011

Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology.
Proceedings of the IEEE International Conference on Acoustics, 2011

System perspective on embedded multimedia.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Seizure prediction based on classification of EEG synchronization patterns with on-line retraining and post-processing scheme.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Mobile energy expenditure tracking system based on heart rate and motion providing extra extensions for personalized care.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Robust heart rate measurement with phonocardiogram by on-line template extraction and matching.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor for mobile multimedia applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension.
Signal Processing Systems, 2010

Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition.
IEEE Trans. Circuits Syst. Video Techn., 2010

A novel 2Dd-to-3D conversion system using edge information.
IEEE Trans. Consumer Electronics, 2010

A 212 MPixels/s 4096 ˟ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications.
J. Solid-State Circuits, 2010

Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis.
J. Solid-State Circuits, 2010

Localized Detection of Abandoned Luggage.
EURASIP J. Adv. Sig. Proc., 2010

Video encoder design for high-definition 3D video communication systems.
IEEE Communications Magazine, 2010

A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A multimedia semantic analysis SoC (SASoC) with machine-learning engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Hybrid color compensation for virtual view synthesis in multiview video applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-cost hardware architecture design for 3D warping engine in multiview video applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low bandwidth decoder framework for H.264/AVC scalable extension.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Architecture design of stereo matching using belief propagation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Accuracy and power tradeoff in spike sorting microsystems with cubic spline interpolation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Learning-Based Vehicle Detection Using Up-Scaling Schemes and Predictive Frame Pipeline Structures.
Proceedings of the 20th International Conference on Pattern Recognition, 2010

An exploration of on-road vehicle detection using hierarchical scaling schemes.
Proceedings of the International Conference on Image Processing, 2010

Efficient message reduction algorithm for stereo matching using belief propagation.
Proceedings of the International Conference on Image Processing, 2010

Video stabilization for vehicular applications using SURF-like descriptor and KD-tree.
Proceedings of the International Conference on Image Processing, 2010

A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Video Compression.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System.
IEEE Trans. Circuits Syst. Video Techn., 2009

Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices.
IEEE Trans. Circuits Syst. Video Techn., 2009

Plenary presentation B.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Mapping Scalable Video Coding decoder on multi-core stream processors.
Proceedings of the 2009 Picture Coding Symposium, 2009

A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A Branch Selection Multi-symbol High throughput CABAC Decoder Architecture for H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

On-chip Principal Component Analysis with a Mean Pre-estimation Method for Spike Sorting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Algorithm and architecture for object tracking using particle filter.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Cache-based integer motion/disparity estimation for quad-HD H.264/AVC and HD multiview video coding.
Proceedings of the IEEE International Conference on Acoustics, 2009

Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control.
Proceedings of the IEEE International Conference on Acoustics, 2009

Fast belief propagation process element for high-quality stereo estimation.
Proceedings of the IEEE International Conference on Acoustics, 2009

Hardware-efficient belief propagation.
Proceedings of the 2009 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2009), 2009

Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysis.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder.
Signal Processing Systems, 2008

VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC.
Signal Processing Systems, 2008

Analysis and Hardware Architecture Design of Global Motion Estimation.
Signal Processing Systems, 2008

Content-Aware Prediction Algorithm With Inter-View Mode Decision for Multiview Video Coding.
IEEE Trans. Multimedia, 2008

Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Techn., 2008

Architecture design of full HD JPEG XR encoder for digital photography applications.
IEEE Trans. Consumer Electronics, 2008

Bio-inspired unified model of visual segmentation system for CAPTCHA character recognition.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Analysis of belief propagation for hardware realization.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Intelligent Content-Aware Model-Free Low Power Evoked Neural Signal Compression.
Proceedings of the Advances in Multimedia Information Processing, 2008

iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A cost effective reconfigurable memory for multimedia multithreading streaming architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Frame-parallel design strategy for high definition B-frame H.264/AVC encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Spatial-temporal consistent labeling for multi-camera multi-object surveillance systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Multiview video hybrid coding system with texture-depth synthesis.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Scalable video adaptation optimization using soft decision scheme.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Architecture design of high performance embedded compression for high definition video coding.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

A 100 MHz 1920×1080 HD-Photo 20 frames/sec JPEG XR encoder design.
Proceedings of the International Conference on Image Processing, 2008

A real-time augmented view synthesis system for transparent car pillars.
Proceedings of the International Conference on Image Processing, 2008

Fast motion estimation with inter-view motion vector prediction for stereo and multiview video coding.
Proceedings of the IEEE International Conference on Acoustics, 2008

Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC.
Proceedings of the IEEE International Conference on Acoustics, 2008

iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.
Proceedings of the 45th Design Automation Conference, 2008

A Localized Approach to Abandoned Luggage Detection with Foreground-Mask Sampling.
Proceedings of the Fifth IEEE International Conference on Advanced Video and Signal Based Surveillance, 2008

Priority depth fusion for the 2D to 3D conversion system.
Proceedings of the Conference on Three-Dimensional Image Capture and Applications 2008, 2008

2007
Word-Level Parallel Architecture of JPEG 2000 Embedded Block Coding Decoder.
IEEE Trans. Multimedia, 2007

On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Techn., 2007

Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC.
IEEE Trans. Circuits Syst. Video Techn., 2007

Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC.
IEEE Trans. Circuits Syst. Video Techn., 2007

124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory.
IEEE Trans. Circuits Syst. Video Techn., 2007

A Quality-of-Experience Video Adaptor for Serving Scalable Video Applications.
IEEE Trans. Consumer Electronics, 2007

Symmetric trinocular dense disparity estimation for car surrounding camera array.
Proceedings of the Visual Communications and Image Processing 2007, 2007

Fast prediction algorithm of adaptive GOP structure for SVC.
Proceedings of the Visual Communications and Image Processing 2007, 2007

Fast luminance and chrominance correction based on motion compensated linear regression for multi-view video coding.
Proceedings of the Visual Communications and Image Processing 2007, 2007

Reconfigurable architecture for video applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Multimedia and Parrallel Signal Processors.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Depth Map Generation for 2D-to-3D Conversion by Short-Term Motion Assisted Color Segmentation.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results.
VLSI Signal Processing, 2006

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems.
VLSI Signal Processing, 2006

Interactive Content-aware Video Streaming System with Fine Granularity Scalability.
VLSI Signal Processing, 2006

Platform-Based MPEG-4 SOC Design for Video Communications.
VLSI Signal Processing, 2006

High-Performance JPEG 2000 Encoder With Rate-Distortion Optimization.
IEEE Trans. Multimedia, 2006

Precompression Quality-Control Algorithm for JPEG 2000.
IEEE Trans. Image Processing, 2006

Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC.
IEEE Trans. Circuits Syst. Video Techn., 2006

Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems.
IEEE Trans. Circuits Syst. Video Techn., 2006

Level C+ data reuse scheme for motion estimation with corresponding coding orders.
IEEE Trans. Circuits Syst. Video Techn., 2006

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder.
IEEE Trans. Circuits Syst. Video Techn., 2006

Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC.
IEEE Trans. on Circuits and Systems, 2006

Analysis and architecture design of variable block-size motion estimation for H.264/AVC.
IEEE Trans. on Circuits and Systems, 2006

Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Analysis and VLSI architecture of update step in motion-compensated temporal filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low power and power aware fractional motion estimation of H.264/AVC for mobile applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Analysis of scalable architecture for the embedded block coding in JPEG 2000.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Frame-level data reuse for motion-compensated temporal filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Real-Time Depth Image based Rendering Hardware Accelerator for Advanced Three Dimensional Television System.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Relative Depth Layer Extraction for Monoscopic Video by Use of Multidimensional Filter.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Line Buffer Wordlength Analysis for Line-Based 2-D DWT.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Design and Implementation Of Word-Level Embedded Block Coding Architecture in JPEG 2000 Decoder.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Dances with multimedia: embedded video codec design.
Proceedings of the 2006 International Conference on Compilers, 2006

Hardware architecture design of an H.264/AVC video codec.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.
VLSI Signal Processing, 2005

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.
VLSI Signal Processing, 2005

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.
VLSI Signal Processing, 2005

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System.
VLSI Signal Processing, 2005

Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform.
IEEE Trans. Signal Processing, 2005

Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method.
IEEE Trans. Circuits Syst. Video Techn., 2005

Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder.
IEEE Trans. Circuits Syst. Video Techn., 2005

Parallel embedded block coding architecture for JPEG 2000.
IEEE Trans. Circuits Syst. Video Techn., 2005

Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements.
IEEE Trans. Circuits Syst. Video Techn., 2005

Video de-interlacing by adaptive 4-field global/local motion compensated approach.
IEEE Trans. Circuits Syst. Video Techn., 2005

Fast decomposition of filterbanks for the state-of-the-art audio coding.
IEEE Signal Process. Lett., 2005

Advances in Hardware Architectures for Image and Video Coding - A Survey.
Proceedings of the IEEE, 2005

Special Issue on Advances in Video Coding and Delivery.
Proceedings of the IEEE, 2005

Feature-Based Error Concealment for Object-Based Video.
IEICE Transactions, 2005

Hardware architecture design of video compression for multimedia communication systems.
IEEE Communications Magazine, 2005

Reconfigurable Platform for Content Science Research.
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Application Layer Error Correction Scheme for Video Header Protection on Wireless Network.
Proceedings of the Seventh IEEE International Symposium on Multimedia (ISM 2005), 2005

One-pass computation-aware motion estimation with adaptive search strategy.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Memory and computationally efficient psychoacoustic model for MPEG AAC on 16-bit fixed-point processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Stereo video coding system with hybrid coding based on joint prediction scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Architecture of global motion compensation for MPEG-4 advanced simple profile.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

Efficient Depth Image Based Rendering with Edge Dependent Depth Filter and Interpolation.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

System analysis of VLSI architecture for motion-compensated temporal filtering.
Proceedings of the 2005 International Conference on Image Processing, 2005

Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Memory efficient JPEG2000 architecture with stripe pipeline scheme.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Four field variable block size motion compensated adaptive de-interlacing.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

PEG, MPEG-4, and H.264 Codec IP Development.
Proceedings of the 2005 Design, 2005

2004
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
IEEE Trans. Signal Processing, 2004

Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques.
IEEE Trans. Multimedia, 2004

Global elimination algorithm and architecture design for fast block matching motion estimation.
IEEE Trans. Circuits Syst. Video Techn., 2004

A low complexity design of psycho-acoustic model for MPEG-2/4 advanced audio coding.
IEEE Trans. Consumer Electronics, 2004

Power-efficient FIR filter architecture design for wireless embedded system.
IEEE Trans. on Circuits and Systems, 2004

Novel precompression rate-distortion optimization algorithm for JPEG 2000.
Proceedings of the Visual Communications and Image Processing 2004, 2004

Architecture and Analysis of Color Structure Descriptor for Real-Time Video Indexing and Retrieval.
Proceedings of the Advances in Multimedia Information Processing - PCM 2004, 5th Pacific Rim Conference on Multimedia, Tokyo, Japan, November 30, 2004

MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Reconfigurable discrete cosine transform processor for object-based video signal processing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-power parallel tree architecture for full search block-matching motion estimation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

B-spline factorization-based architecture for inverse discrete wavelet transform.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hardware architecture design for H.264/AVC intra frame coder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Extended intelligent edge-based line average with its implementation and test method.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Architecture of MPEG-7 color structure description generator for realtime video applications.
Proceedings of the 2004 International Conference on Image Processing, 2004

Parallel global elimination algorithm and architecture design for fast block matching motion estimation.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Memory analysis and architecture for two-dimensional discrete wavelet transform.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Four field local motion compensated de-interlacing.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000.
IEEE Trans. Circuits Syst. Video Techn., 2003

Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors.
IEEE Trans. Circuits Syst. Video Techn., 2003

Predictive watershed: a fast watershed algorithm for video segmentation.
IEEE Trans. Circuits Syst. Video Techn., 2003

Motion adaptive interpolation with horizontal motion detection for deinterlacing.
IEEE Trans. Consumer Electronics, 2003

Error concealment algorithm using interested direction for JPEG 2000 image transmission.
IEEE Trans. Consumer Electronics, 2003

Fast motion estimation algorithm for H.264/MPEG-4 AVC by using multiple reference frame skipping criteria.
Proceedings of the Visual Communications and Image Processing 2003, 2003

Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach.
Proceedings of the Visual Communications and Image Processing 2003, 2003

Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Motion adaptive de-interlacing by horizontal motion detection and enhanced ELA processing.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

High speed memory efficient EBCOT architecture for JPEG2000.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Effective hardware-oriented technique for the rate control of JPEG2000 encoding.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Performance analysis of hardware oriented algorithm modification in H.264.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Analysis and reduction of reference frames for motion estimation in MPEG-4 AVC/JVT/H.264.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Architecture design for deblocking filter in H.264/JVT/AVC.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Novel word-level algorithm of embedded block coding in JPEG 2000.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Hardware oriented rate control algorithm and implementation for realtime video coding.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Unsupervised object-based sprite coding system for tennis sport.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.
Proceedings of the 2003 International Conference on Image Processing, 2003

Efficient stereo video coding system for immersive teleconference with two-stage hybrid disparity estimation algorithm.
Proceedings of the 2003 International Conference on Image Processing, 2003

Platform architecture design for MEG-4 video coding.
Proceedings of the 2003 International Conference on Image Processing, 2003

Motion compensated de-interlacing with adaptive global motion estimation and compensation.
Proceedings of the 2003 International Conference on Image Processing, 2003

Performance analysis of hardware oriented algorithm modifications in H.264.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Analysis and reduction of reference frames for motion estimation in MPEG-4 AVC/JVT/H.264.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Hardware oriented rate control algorithm and implementation for realtime video coding.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Low-delay and error-robust wireless video transmission for video communications.
IEEE Trans. Circuits Syst. Video Techn., 2002

Efficient moving object segmentation algorithm using background registration technique.
IEEE Trans. Circuits Syst. Video Techn., 2002

VLSI architecture design of MPEG-4 shape coding.
IEEE Trans. Circuits Syst. Video Techn., 2002

VLSI implementation of shape-adaptive discrete wavelet transform.
Proceedings of the Visual Communications and Image Processing 2002, 2002

Automatic threshold decision of background registration technique for video segmentation.
Proceedings of the Visual Communications and Image Processing 2002, 2002

Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A hardware accelerator for video segmentation using programmable morphology PE array.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low delay, error robust wireless video transmission architecture for video communication.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

Bit-plane error recovery via cross subband for image transmission in JPEG2000.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

Simple and effective algorithm for automatic tracking of a single object using a pan-tilt-zoom camera.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

Multiple sprites and frame skipping techniques for sprite generation with high subjective quality and fast speed.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

A fast and high subjective quality sprite generation algorithm with frame skipping and multiple sprites techniques.
Proceedings of the 2002 International Conference on Image Processing, 2002

Computation reduction technique for lossy JPEG2000 encoding through EBCOT Tier-2 feedback processing.
Proceedings of the 2002 International Conference on Image Processing, 2002

An efficient and low power architecture design for motion estimation using global elimination algorithm.
Proceedings of the IEEE International Conference on Acoustics, 2002

Predictive watershed for image sequences segmentation.
Proceedings of the IEEE International Conference on Acoustics, 2002

Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Error recovery for MPEG-4 shape and texture information.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Real-time deblocking filter for MPEG-4 systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core.
VLSI Signal Processing, 2001

A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform.
VLSI Signal Processing, 2001

Guest Editors' Introduction.
VLSI Signal Processing, 2001

An efficient architecture for two-dimensional discrete wavelet transform.
IEEE Trans. Circuits Syst. Video Techn., 2001

A novel low-power full-search block-matching motion-estimation design for H.263+.
IEEE Trans. Circuits Syst. Video Techn., 2001

CDSP: an application-specific digital signal processor for third generation wireless communications.
IEEE Trans. Consumer Electronics, 2001

Efficient architecture of binary motion estimation for MPEG-4 shape coding.
Proceedings of the Visual Communications and Image Processing 2001, 2001

Lifting based discrete wavelet transform architecture for JPEG2000.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Scalable module-based architecture for MPEG-4 BMA motion estimation.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A hybrid morphology processing units architecture for real-time video segmentation systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Analysis and architecture design of EBCOT for JPEG-2000.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Automatic Video Segmentation For MPEG-4 Using Predictivewatershed.
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001

Analysis and Architecture Design of JPEG2000.
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001

Error-Propagation Analysis and Concealment Strategy for MPEG-4 Video Bitstream with Data Partitioning.
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001

Partial-result-reuse architecture and its design technique for morphological operations.
Proceedings of the IEEE International Conference on Acoustics, 2001

Design and implementation of JPEG encoder IP core.
Proceedings of ASP-DAC 2001, 2001

2000
A Low Power 8 x 8 Direct 2-D DCT Chip Design.
VLSI Signal Processing, 2000

System design consideration for digital wheelchair controller.
IEEE Trans. Industrial Electronics, 2000

Efficient video segmentation algorithm for real-time MPEG-4 camera system.
Proceedings of the Visual Communications and Image Processing 2000, 2000

A programmable VLSI architecture for 2-D discrete wavelet transform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

MPEG-4 video bitstream structure analysis and its parsing architecture design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Performance analysis and architecture evaluation of MPEG-4 video codec system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A LOG-EXP still image compression chip design.
IEEE Trans. Consumer Electronics, 1999

A cost effective architecture design of inverse quantization and multichannel processing for MPEG-2 audio decoding.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low power full-search block-matching motion estimation chip for H.263+.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A novel image compression algorithm by using Log-Exp transform.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A VLSI architecture design of VLC encoder for high data rate video/image coding.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm.
IEEE Trans. Circuits Syst. Video Techn., 1998

A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm.
Proceedings of the ASP-DAC '98, 1998

1997
Jointly Optimal Region-Classified Adaptive Vector Quantization for Very Low Bit Rate Video Coding.
VLSI Signal Processing, 1997

A bit-level pipelined VLSI architecture for the running order algorithm.
IEEE Trans. Signal Processing, 1997

A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method.
IEEE Trans. Circuits Syst. Video Techn., 1997

Error concealment of lost motion vectors with overlapped motion compensation.
IEEE Trans. Circuits Syst. Video Techn., 1997

Error Resilience for Block Loss with Overlapped Motion Compensation.
Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997

A flexible data-interlacing architecture for full-search block-matching algorithm.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
A 32-bit logarithmic number system processor.
VLSI Signal Processing, 1996

Scalable implementation scheme for multirate FIR filters and its application in efficient design of subband filter banks.
IEEE Trans. Circuits Syst. Video Techn., 1996

Design strategy for three-dimensional subband filter banks.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

A pseudo-object-oriented very low bit-rate video coding system with cache VQ for detail compensation.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

A self-adjusting weighted median filter for removing impulse noise in images.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

Building a pseudo object-oriented very low bit-rate video coding system from a modified optical flow motion estimation algorithm.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

A very low bit rate video coding system using adaptive region-classified vector quantization.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995
Pipeline interleaving design for FIR, IIR, and FFT array processors.
VLSI Signal Processing, 1995

High throughput CORDIC-based systolic array design for the discrete cosine transform.
IEEE Trans. Circuits Syst. Video Techn., 1995

A new block-matching criterion for motion estimation and its implementation.
IEEE Trans. Circuits Syst. Video Techn., 1995

A hardware-oriented design for weighted median filters.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Rate-optimal DSP synthesis by pipeline and minimum unfolding.
IEEE Trans. VLSI Syst., 1994

Parallel architectures for 3-step hierarchical search block-matching algorithm.
IEEE Trans. Circuits Syst. Video Techn., 1994

Accuracy improvement and cost reduction of 3-step search block matching algorithm for video coding.
IEEE Trans. Circuits Syst. Video Techn., 1994

A high quality MC-OBTC Codec for video signal processing.
IEEE Trans. Circuits Syst. Video Techn., 1994

One-dimensional full search motion estimation algorithm for video coding.
IEEE Trans. Circuits Syst. Video Techn., 1994

Vector quantization using tree-structured self-organizing feature maps.
IEEE Journal on Selected Areas in Communications, 1994

Tree-Structure Architecture and VLSI Implementation for Vector Quantization Algorithms.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Parallel Architectures of 3-Step Search Block-Matching Algorithm for Video Coding.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

The Chip Design of A 32-b Logarithmic Number System.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
An efficient and simple VLSI tree architecture for motion estimation algorithms.
IEEE Trans. Signal Processing, 1993

Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Hardware Verification Using Symbolic State Transition Graphs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
Design of Concurrent Error-Detectable VLSI-Based Array Dividers.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
An efficient parallel motion estimation algorithm for digital image processing.
IEEE Trans. Circuits Syst. Video Techn., 1991

ASG: Automatic schematic generator.
Integration, 1991

A Predictive Parallel Motion Estimation Algorithm for Digital Image Processing.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

An automatic synthesizer for CMOS operational amplifiers.
Proceedings of the conference on European design automation, 1991


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