Chao-Tsung Huang
Orcid: 0000-0002-9173-520XAffiliations:
- National Tsing Hua University, Taiwan
According to our database1,
Chao-Tsung Huang
authored at least 57 papers
between 2002 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Biased Mixed-Precision Convolution Engine for Hardware-Efficient Computational Imaging CNN.
Proceedings of the Asia Pacific Signal and Information Processing Association Annual Summit and Conference, 2023
2022
Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Globally Assisted Instance Normalization for Bandwidth-Efficient Neural Style Transfer.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Ernet Family: Hardware-Oriented Cnn Models For Computational Imaging Using Block-Based Inference.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
2019
Empirical Bayesian Light-Field Stereo Matching by Robust Pseudo Random Field Modeling.
IEEE Trans. Pattern Anal. Mach. Intell., 2019
A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
2018
A 320M Pixel/S Vlsi Architecture Design of Weighted Mode Filter for 4K Ultra-Hd Depth Upsampling.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation.
IEEE Trans. Image Process., 2017
Proceedings of the IEEE International Conference on Computer Vision, 2017
2016
Fast Distribution Fitting for Parameter Estimation of Range-Weighted Neighborhood Filters.
IEEE Signal Process. Lett., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Image Process., 2015
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
2014
Proceedings of the High Efficiency Video Coding (HEVC), Algorithms and Architectures, 2014
Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE J. Solid State Circuits, 2014
Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
2013
Proceedings of the 2013 Visual Communications and Image Processing, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2007
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Technol., 2007
2006
System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering.
IEEE Trans. Signal Process., 2006
IEEE Trans. Multim., 2006
IEEE Trans. Circuits Syst. Video Technol., 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
2005
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.
J. VLSI Signal Process., 2005
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.
J. VLSI Signal Process., 2005
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.
J. VLSI Signal Process., 2005
IEEE Trans. Signal Process., 2005
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method.
IEEE Trans. Circuits Syst. Video Technol., 2005
Proc. IEEE, 2005
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 International Conference on Image Processing, 2005
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
IEEE Trans. Signal Process., 2004
Reconfigurable discrete cosine transform processor for object-based video signal processing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
B-spline factorization-based architecture for inverse discrete wavelet transform.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
2003
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.
Proceedings of the 2003 International Conference on Image Processing, 2003
2002
VLSI implementation of shape-adaptive discrete wavelet transform.
Proceedings of the Visual Communications and Image Processing 2002, 2002
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002