Chuanlei Zheng

According to our database, Chuanlei Zheng authored at least 7 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

The Initial Performance Evaluation of Mixed Multi-Frequency Undifferenced and Uncombined BDS-2/3 Precise Point Positioning under Urban Environmental Conditions.

Fuxin Yang, Chuanlei Zheng, Jie Zhang, Zhiguo Sun, Liang Li, Lin Zhao

Remote. Sens., 2022

2021

Continuity Enhancement Method for Real-Time PPP Based on Zero-Baseline Constraint of Multi-Receiver.

Fuxin Yang, Chuanlei Zheng, Hui Li, Liang Li, Jie Zhang, Lin Zhao

Remote. Sens., 2021

2016

Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing.

Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan

J. Circuits Syst. Comput., 2016

2014

Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors.

Chuanlei Zheng, Shuai Wang

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

Combating NBTI-induced aging in data caches.

Shuai Wang, Guangshan Duan, Chuanlei Zheng, Tao Jin

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors.

Chuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Low power aging-aware register file design by duty cycle balancing.

Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012