Jie S. Hu

IEEE Trans. Very Large Scale Integr. Syst., 2012

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

On the Thermal Attack in Instruction Caches.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2010

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2009

On the Exploitation of Narrow-Width Values for Improving Register File Reliability.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Compiler-assisted soft error detection under performance and energy constraints in embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2009

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

Exploiting narrow-width values for thermal-aware register file designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Self-Adaptive Data Caches for Soft-Error Reliability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Asymmetrically banked value-aware register files for low-energy and high-performance.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

BTB Access Filtering: A Low Energy and High Performance Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Reconfiguration support for vector operations.

[BibT_eX]

[DOI]

Hongyan Yang

Int. J. High Perform. Syst. Archit., 2007

Optimising power efficiency in trace cache fetch unit.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

FPGA-based Vector Processing for Matrix Operations.

[BibT_eX]

[DOI]

Hongyan Yang

Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Vector Processing Support for FPGA-Oriented High Performance Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Asymmetrically Banked Value-Aware Register Files.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors.

[BibT_eX]

Xiaofang Wang

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006

On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005

Analyzing data reuse for cache reconfiguration.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2005

Optimizing the Thermal Behavior of Subarrayed Data Caches.

[BibT_eX]

[DOI]

Johnsy K. John

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Compiler-Directed Instruction Duplication for Soft Error Detection.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004

Reducing instruction cache energy consumption using a compiler-based strategy.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2004

Exploring Wakeup-Free Instruction Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Scheduling Reusable Instructions for Power Reduction.

[BibT_eX]

[DOI]

Soontae Kim

Proceedings of the 2004 Design, 2004

2003

Leakage Current: Moore's Law Meets Static Power.

[BibT_eX]

[DOI]

Computer, 2003

Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Exploiting program hotspots and code sequentiality for instruction cache leakage management.

[BibT_eX]

[DOI]

A. Nadgir

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002

Compiler-directed instruction cache leakage optimization.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Energy-conscious compilation based on voltage scaling.

[BibT_eX]

[DOI]

Hendra Saputra

Proceedings of the 2002 Joint Conference on Languages, 2002

Compiler-directed cache polymorphism.

[BibT_eX]

[DOI]

Hendra Saputra

Wei Zhang

Proceedings of the 2002 Joint Conference on Languages, 2002

Power-Efficient Trace Caches.

[BibT_eX]

[DOI]