Guangshan Duan

According to our database, Guangshan Duan authored at least 7 papers between 2012 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors.

Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas

Proceedings of the IEEE International Test Conference, 2020

2017

Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime.

Shuai Wang, Guangshan Duan, Yupeng Li, Qianhao Dong

ACM Trans. Design Autom. Electr. Syst., 2017

2016

Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing.

Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan

J. Circuits Syst. Comput., 2016

2015

On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors.

Shuai Wang, Guangshan Duan

Microprocess. Microsystems, 2015

2014

Exploiting narrow-width values for improving non-volatile cache lifetime.

Guangshan Duan, Shuai Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Combating NBTI-induced aging in data caches.

Shuai Wang, Guangshan Duan, Chuanlei Zheng, Tao Jin

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Low power aging-aware register file design by duty cycle balancing.

Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012