Chuanning Wang
Orcid: 0009-0000-0301-9274
According to our database1,
Chuanning Wang authored at least 7 papers
between 2023 and 2026.
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Bibliography
2026
Prototypical rectification with interpretable fusion for enhanced industrial defect segmentation.
J. Supercomput., January, 2026
Top-V: A Flexible and Programmable Top-K Acceleration Framework Based on the RISC-V ISA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference.
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
2024
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference.
CoRR, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
SAW: A Robust Watermarking based on Visual Structure Measurement and Spatial-Channel Attention.
Proceedings of the 6th International Conference on Image and Graphics Processing, 2023