Jun Lin

Affiliations:
  • Nanjing University, School of Electronic Science and Engineering, Nanjing, China
  • Lehigh University, Bethlehem, PA, USA (PhD 2015)


According to our database1, Jun Lin authored at least 155 papers between 2008 and 2024.

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Bibliography

2024
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes.
CoRR, 2024

A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference.
CoRR, 2024

2023
An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT.
IEEE Trans. Signal Process., 2023

A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge.
CoRR, 2023

An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022
Rethinking Adaptive Computing: Building a Unified Model Complexity-Reduction Framework With Adversarial Robustness.
IEEE Trans. Neural Networks Learn. Syst., 2022

A Proximal Iteratively Reweighted Approach for Efficient Network Sparsification.
IEEE Trans. Computers, 2022

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation.
IEEE Trans. Computers, 2022

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT.
CoRR, 2022

Forecasting Stock Indexes with Metabolic DWT and MWA-GM(1,1).
Proceedings of the 14th International Conference on Wireless Communications and Signal Processing, 2022

An Efficient FPGA Accelerator for Point Cloud.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Accelerate Three-Dimensional Generative Adversarial Networks Using Fast Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Efficient Hardware Accelerator for Sparse Transformer Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Magical-Decomposition: Winning Both Adversarial Robustness and Efficiency on Hardware.
Proceedings of the International Conference on Machine Learning and Cybernetics, 2022

An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., 2021

An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Evaluations on Deep Neural Networks Training Using Posit Number System.
IEEE Trans. Computers, 2021

An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes.
IEEE Commun. Lett., 2021

Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Information Storage Bit-Flipping Decoder for LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning.
IEEE Trans. Circuits Syst., 2020

Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator.
IEEE Trans. Circuits Syst., 2020

Fine-Grained Bit-Flipping Decoding for LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A lightweight face detector by integrating the convolutional neural network with the image pyramid.
Pattern Recognit. Lett., 2020

Multi-Layer Generalized Integrated Interleaved Codes.
IEEE Commun. Lett., 2020

Faster Software Implementation of the SIKE Protocol Based on A New Data Representation.
IACR Cryptol. ePrint Arch., 2020

Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2020

Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Temporal Residual Feature Learning for Efficient 3D Convolutional Neural Network on Action Recognition Task.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

A Reconfigurable DNN Training Accelerator on FPGA.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

A Serial Maximum-likelihood Detection Algorithm for Massive MIMO Systems.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

A Computation-Efficient Solution for Acceleration of Generative Adversarial Network.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Exploring Quantization in Few-Shot Learning.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

In-Memory Computing: The Next-Generation AI Computing Paradigm.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

Efficient FPGA design for Convolutions in CNN based on FFT-pruning.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Improved Fast-SSC-Flip Decoding of Polar Codes.
IEEE Commun. Lett., 2019

Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders.
IEEE Commun. Lett., 2019

High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2019

E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm.
CoRR, 2019

Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes.
IEEE Access, 2019

A Hardware-Oriented and Memory-Efficient Method for CTC Decoding.
IEEE Access, 2019

Training Deep Neural Networks Using Posit Number System.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Hybrid Preconditioned CG Detection with Sequential Update for Massive MIMO Systems.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Low-Complexity Error-and-Erasure Decoding Algorithm for t=2 RS Codes.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes.
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Methodology for Efficient Reconfigurable Architecture of Generative Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

TIE: energy-efficient tensor train-based inference engine for deep neural network.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

A New Fast-SSC-Flip Decoding of Polar Codes.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019

Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Enhanced Offset Min-Sum decoder for 5G LDPC Codes.
Proceedings of the 25th Asia-Pacific Conference on Communications, 2019

2018
Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems.
IEEE Wirel. Commun. Lett., 2018

A Stage-Combined Belief Propagation Decoder for Polar Codes.
J. Signal Process. Syst., 2018

An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Efficient Hardware Architectures for Deep Convolutional Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference.
IEEE Signal Process. Lett., 2018

Parameter-Free ℓ<sub>p</sub>-Box Decoding of LDPC Codes.
IEEE Commun. Lett., 2018

SGAD: Soft-Guided Adaptively-Dropped Neural Network.
CoRR, 2018

Approximate Comparator: Design and Analysis.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Bandwidth Efficient Architectures for Convolutional Neural Network.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

A Low-Complexity Massive MIMO Detection Algorithm Based on Matrix Partition.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Optimized Architecture For Decomposed Convolutional Neural Networks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A New Soft-input Hard-output decoding algorithm for Turbo Product Codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Approximate Belief Propagation Decoder for Polar Codes.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Fast and Low-Complexity Decoding Algorithm and Architecture for Quadruple-Error-Correcting RS codes.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A Novel Compiler for Regular Expression Matching Engine Construction.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Efficient Reconfigurable Hardware Core for Convolutional Neural Networks.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Efficient Soft Cancelation Decoder Architectures for Polar Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Optimized sorting network for successive cancellation list decoding of polar codes.
IEICE Electron. Express, 2017

An access pattern based adaptive mapping function for GPGPU scratchpad memory.
IEICE Electron. Express, 2017

Reduced complexity message passing detection algorithm in large-scale MIMO systems.
Proceedings of the 9th International Conference on Wireless Communications and Signal Processing, 2017

Low-complexity detection algorithms based on matrix partition for massive MIMO.
Proceedings of the 9th International Conference on Wireless Communications and Signal Processing, 2017

Efficient approximate layered LDPC decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Energy efficient SVM classifier using approximate computing.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Multimode Area-Efficient SCL Polar Decoder.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A High Throughput List Decoder Architecture for Polar Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Symbol-Decision Successive Cancellation List Decoder for Polar Codes.
IEEE Trans. Signal Process., 2016

Design and implementation of high performance matrix inversion based on reconfigurable processor.
IEICE Electron. Express, 2016

An ultra-long FFT architecture implemented in a reconfigurable application specified processor.
IEICE Electron. Express, 2016

Efficient convolution architectures for convolutional neural network.
Proceedings of the 8th International Conference on Wireless Communications & Signal Processing, 2016

Intra-layer nonuniform quantization of convolutional neural network.
Proceedings of the 8th International Conference on Wireless Communications & Signal Processing, 2016

An Efficient Hardware Architecture for Lossless Data Compression in Data Center.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Stage-combined belief propagation decoding of polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A high throughput belief propagation decoder architecture for polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Error performance analysis of the symbol-decision SC polar decoder.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

2015
An Efficient List Decoder Architecture for Polar Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient approximate ML decoding units for polar list decoders.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Reduced complexity belief propagation decoders for polar codes.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

A hybrid partial sum computation unit architecture for list decoders of polar codes.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014
Efficient Error Control Decoder Architectures for Noncoherent Random Linear Network Coding.
J. Signal Process. Syst., 2014

An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Symbol-based successive cancellation list decoder for polar codes.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

A reduced latency list decoding algorithm for polar codes.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Efficient list decoder architecture for polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Linearized Polynomial Interpolation and Its Applications.
IEEE Trans. Signal Process., 2013

A decoding algorithm with reduced complexity for non-binary LDPC codes over large fields.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Reduced-Complexity Decoders of Long Reed-Solomon Codes Based on Composite Cyclotomic Fourier Transforms.
IEEE Trans. Signal Process., 2012

Efficient Kötter-Kschischang Decoder Architectures for Noncoherent Error Control in Random Linear Network Coding.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Modified shuffled schedule for nonbinary low-density parity-check codes.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010
Flexible LDPC Decoder Design for Multigigabit-per-Second Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An Efficient VLSI Architecture for Nonbinary LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
LDPC decoder design for high rate wireless personal area networks.
IEEE Trans. Consumer Electron., 2009

Decoder Design for RS-Based LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

An improved min-sum based column-layered decoding algorithm for LDPC codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

LDPC Decoder Design for IEEE 802.15 Standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Low-complexity shift-LDPC decoder for high-speed communication systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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