Zhongfeng Wang

This page is a disambiguation page, it actually contains multiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2026
Beyond Geometry: Efficient Topologically-Grounded Navigation in Complex 3D Environments.
CoRR, May, 2026

High-Throughput and Configurable Modular Multiplier Using Extended Montgomery Reduction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

Top-V: A Flexible and Programmable Top-K Acceleration Framework Based on the RISC-V ISA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

SnipSnap: A Joint Compression Format and Dataflow Co-Optimization Framework for Efficient Sparse LLM Accelerator Design.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
A One-time Self Calibration Technique for Open-loop FIA in Noise Shaping SAR Achieving Ultra Gain PVT-robustness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Parameter-Efficient Fine-Tuning with Circulant and Diagonal Vectors.
Proceedings of the Thirty-Fourth International Joint Conference on Artificial Intelligence, 2025


StripDet: Strip Attention-Based Lightweight 3D Object Detection from Point Cloud.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

A Memory-Efficient Framework for Deformable Transformer with Neural Architecture Search.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024
Versatile Low-Frequency Magnetoelectric Antenna With Memory in Computing Ability and Internet of Underground Things Application.
IEEE Internet Things J., October, 2024

ECR: An Expertise-Enriched Conclude-Then-Refine Summarization Framework for Professional Articles.
Proceedings of the Natural Language Processing and Information Systems, 2024

A 14-bit 6GS/s DAC Achieving >65dBc SFDR with Bilateral Output Impedance Compensation in 22nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
POLYCORN: Data-driven Cross-layer Multipath Networking for High-speed Railway through Composable Schedulerlets.
Proceedings of the 20th USENIX Symposium on Networked Systems Design and Implementation, 2023

2022
Analysis of the Effect of Demand-Driven Dynamic Parking Pricing on on-Street Parking Demand.
IEEE Access, 2022

2021
Learning Robust and Lightweight Model through Separable Structured Transformations.
CoRR, 2021

2020
The Application of Improving Particle Group Algorithm in Logistics Path Optimization.
Proceedings of the 5th IEEE International Conference on Intelligent Transportation Engineering, 2020

2019
An Active-Passive Measurement Study of TCP Performance over LTE on High-speed Rails.
Proceedings of the 25th Annual International Conference on Mobile Computing and Networking, 2019

Combinatorial Turbofan Engine Agent and Short Take-off and Vertical Landing (STOVL) Aircraft in 5G OGCE.
Proceedings of the 6th International Conference on Systems and Informatics, 2019

2018
An Architecture of System of Systems (SoS) for Commercial Flight Security in 5G OGCE.
Proceedings of the 5th International Conference on Systems and Informatics, 2018

2017
A heterogeneous large-scale parallel SCADA/DCS architecture in 5G OGCE.
Proceedings of the 10th International Congress on Image and Signal Processing, 2017

2013
Next generation backplane and copper cable challenges.
IEEE Commun. Mag., 2013

2012
Super-FEC Codes for 40/100 Gbps Networking.
IEEE Commun. Lett., 2012

2011
Design of Sequential Elements for Low Power Clocking System.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
An Efficient 4-D 8PSK TCM Decoder Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Learning Restricted Bayesian Network Classifiers with Mixed Non-i.i.d. Sampling.
Proceedings of the ICDMW 2010, 2010

Learning Robust Bayesian Network Classifiers in the Space of Markov Equivalent Classes.
Proceedings of the ICDMW 2010, 2010

2006
Optimal Agendas for Sequential English Auctions with Private and Common Values.
Proceedings of the Agent Computing and Multi-Agent Systems, 2006

2005
Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Low hardware complexity parallel turbo decoder architecture.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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