Zhongfeng Wang

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2023
A multiagent deep deterministic policy gradient-based distributed protection method for distribution network.
Neural Comput. Appl., 2023

POLYCORN: Data-driven Cross-layer Multipath Networking for High-speed Railway through Composable Schedulerlets.
Proceedings of the 20th USENIX Symposium on Networked Systems Design and Implementation, 2023

2022
Low-voltage distribution network topology identification based on constrained least square and graph theory.
Soft Comput., 2022

Analysis of the Effect of Demand-Driven Dynamic Parking Pricing on on-Street Parking Demand.
IEEE Access, 2022

View Dialogue in 2D: A Two-stream Model in Time-speaker Perspective for Dialogue Summarization and beyond.
Proceedings of the 29th International Conference on Computational Linguistics, 2022

2021
Learning Robust and Lightweight Model through Separable Structured Transformations.
CoRR, 2021

2020
The Application of Improving Particle Group Algorithm in Logistics Path Optimization.
Proceedings of the 5th IEEE International Conference on Intelligent Transportation Engineering, 2020

2019
Power System Anomaly Detection Based on OCSVM Optimized by Improved Particle Swarm Optimization.
IEEE Access, 2019

An Active-Passive Measurement Study of TCP Performance over LTE on High-speed Rails.
Proceedings of the 25th Annual International Conference on Mobile Computing and Networking, 2019

A Data Quality Improvement Method Based on the Greedy Algorithm.
Proceedings of the Machine Learning and Intelligent Communications, 2019

Data Cleaning Based on Multi-sensor Spatiotemporal Correlation.
Proceedings of the Machine Learning and Intelligent Communications, 2019

Distributed Hierarchical Fault Diagnosis Based on Sparse Auto-Encoder and Random Forest.
Proceedings of the Machine Learning and Intelligent Communications, 2019

Combinatorial Turbofan Engine Agent and Short Take-off and Vertical Landing (STOVL) Aircraft in 5G OGCE.
Proceedings of the 6th International Conference on Systems and Informatics, 2019

Power Consumption and Coverage Test of NB-IoT in the Substation Edge Computing Environment.
Proceedings of the Artificial Intelligence and Security - 5th International Conference, 2019

Towards Edge Computing Based Distributed Data Analytics Framework in Smart Grids.
Proceedings of the Artificial Intelligence and Security - 5th International Conference, 2019

2018
An Architecture of System of Systems (SoS) for Commercial Flight Security in 5G OGCE.
Proceedings of the 5th International Conference on Systems and Informatics, 2018

2017
A heterogeneous large-scale parallel SCADA/DCS architecture in 5G OGCE.
Proceedings of the 10th International Congress on Image and Signal Processing, 2017

2016
Area-efficient scaling-free DFT/FFT design using stochastic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design space exploration for hardware-efficient stochastic computing: A case study on discrete cosine transformation.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

2014
Efficient Decoder Architecture for Single Block-Row Quasi-Cyclic LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Efficient column-layered decoders for single block-row quasi-cyclic LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Area-efficient check node unit architecture for single block-row quasi-cyclic LDPC codes.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Efficient adaptive list successive cancellation decoder for polar codes.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Next generation backplane and copper cable challenges.
IEEE Commun. Mag., 2013

2012
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Super-FEC Codes for 40/100 Gbps Networking.
IEEE Commun. Lett., 2012

2011
Design of Sequential Elements for Low Power Clocking System.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A High-Throughput LDPC Decoder Architecture With Rate Compatibility.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
An Efficient 4-D 8PSK TCM Decoder Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A dual-rate LDPC decoder for china multimedia mobile broadcasting systems.
IEEE Trans. Consumer Electron., 2010

Memory-reduced MAP decoding for double-binary convolutional Turbo code.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Learning Restricted Bayesian Network Classifiers with Mixed Non-i.i.d. Sampling.
Proceedings of the ICDMW 2010, 2010

Learning Robust Bayesian Network Classifiers in the Space of Markov Equivalent Classes.
Proceedings of the ICDMW 2010, 2010

2009
Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2009

High-throughput layered decoder implementation for quasi-cyclic LDPC codes.
IEEE J. Sel. Areas Commun., 2009

High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

High-throughput GCM VLSI Architecture for IEEE 802.1ae Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Error correction for multi-level NAND flash memory using Reed-Solomon codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes.
Proceedings of the 26th International Conference on Computer Design, 2008

2006
Optimal Agendas for Sequential English Auctions with Private and Common Values.
Proceedings of the Agent Computing and Multi-Agent Systems, 2006

2005
Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
On the better protection of short-frame turbo codes.
IEEE Trans. Commun., 2004

2003
High performance, high throughput turbo/SOVA decoder design.
IEEE Trans. Commun., 2003

Low hardware complexity parallel turbo decoder architecture.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Efficient interleaver memory architectures for serial turbo decoding.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Area-efficient high-speed decoding schemes for turbo decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2002

2001
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders.
J. VLSI Signal Process., 2001

On finite precision implementation of low density parity check codes decoder.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Area-efficient high speed decoding schemes for turbo/MAP decoders.
Proceedings of the IEEE International Conference on Acoustics, 2001

A study on the performance, power consumption tradeoffs of short frame turbo decoder design.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Efficient approaches to improving performance of VLSI SOVA-based turbo decoders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Decoding metrics and their applications in VLSI turbo decoders.
Proceedings of the IEEE International Conference on Acoustics, 2000

High throughput low energy FEC/ARQ technique for short frame turbo codes.
Proceedings of the IEEE International Conference on Acoustics, 2000

A K=3, 2 Mbps low power turbo decoder for 3<sup>rd</sup> generation W-CDMA systems.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Area-power-time efficient pipeline-interleaved architectures for wave digital filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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