Ciaran Toal

According to our database, Ciaran Toal authored at least 22 papers between 2003 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

Fully hardware based WFQ architecture for high-speed QoS packet scheduling.

Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen, Sakir Sezer

Integr., 2012

A 1Gbps FPGA-based wireless baseband MIMO transceiver.

Ciaran Toal, Sakir Sezer, Dwayne Burns, Pei Xiao, Vincent F. Fusco

Proceedings of the IEEE 25th International SOC Conference, 2012

2010

Transmit and receive filter design for OFDM based WLAN systems.

Pei Xiao, Ciaran Toal, Dwayne Burns, Vincent F. Fusco, Colin Cowan

Proceedings of the International Conference on Wireless Communications and Signal Processing, 2010

2009

Design and Implementation of a Field Programmable CRC Circuit Architecture.

Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang

IEEE Trans. Very Large Scale Integr. Syst., 2009

2007

Programmable CRC circuit architecture.

Ciaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne Burns, Tiberiu Seceleanu

Proceedings of the 2007 IEEE International SOC Conference, 2007

An FPGA Based Memory Efficient Shared Buffer Implementation.

Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic

Proceedings of the FPL 2007, 2007

An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing.

Ciaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O'Kane

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

FPGA-Based Lookup Circuit for Session-Based IP Packet Classification.

Motasem Abdelghani, Sakir Sezer, Emi Garcia, Jun Mu, Ciaran Toal

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006

Exploration of high performance frame processing architectures.

Ciaran Toal

PhD thesis, 2006

A VLSI GFP Frame Delineation Circuit.

Ciaran Toal, Sakir Sezer, Xin Yang

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Investigation into programmability for layer 2 protocol frame delineation architectures.

Ciaran Toal, Sakir Sezer

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005

Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch.

Stephen O'Kane, Sakir Sezer, Ciaran Toal

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA.

Ciaran Toal, Sakir Sezer

Proceedings of the Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 2005

2004

Exploration of GFP frame delineation architectures for network processing.

Ciaran Toal, Sakir Sezer

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling.

Sakir Sezer, Ciaran Toal, Emi Garcia, Victoria Stewart

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

The Implementation of Scalable ATM Frame Delineation Circuits.

Ciaran Toal, Sakir Sezer

Proceedings of the Telecommunications and Networking, 2004

Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access.

Emi Garcia-Palacios, Sakir Sezer, Ciaran Toal, Stephen Dawson

Proceedings of the Telecommunications and Networking, 2004

Architecture and implementation of a novel tag computation circuit for broadband wireless access packet scheduling.

Sakir Sezer, Emi Garcia-Palacios, Ciaran Toal, Stephen Dawson

Proceedings of IEEE International Conference on Communications, 2004

2003

A 32-Bit SoPC Implementation of a P5.

Ciaran Toal, Sakir Sezer

Proceedings of the Eighth IEEE Symposium on Computers and Communications (ISCC 2003), 30 June, 2003

A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET.

Ciaran Toal, Sakir Sezer

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler.

Brendan McAllister, Sakir Sezer, Ciaran Toal

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Pipelined SoPC Architecture for 2.5 Gbps Network Processing.

Ciaran Toal, Sakir Sezer, Xing Yu

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003