Mike Hutton

According to our database1, Mike Hutton authored at least 41 papers between 1991 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Bibliography

2017
The First 25 Years of the FPL Conference: Significant Papers.
ACM Trans. Reconfigurable Technol. Syst., 2017

2015
Stratix® 10: 14nm FPGA delivering 1GHz.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Significant papers from the first 25 years of the FPL conference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015


2014
Design of a high-density SoC FPGA at 20nm.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2009
FPGA Synthesis and Physical Design.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2008

2007
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Statistical placement for FPGAs considering.
IET Computers & Digital Techniques, 2007

Accelerating pattern matching for DPI.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Equivalence Verification of FPGA and Structured ASIC Implementations.
Proceedings of the FPL 2007, 2007

An FPGA Based Memory Efficient Shared Buffer Implementation.
Proceedings of the FPL 2007, 2007

Integrating FPGAs in high-performance computing: introduction.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2006
Timing model reduction for hierarchical timing analysis.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Placement and Timing for FPGAs Considering Variations.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Architecture Design Methodology.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A methodology for FPGA to structured-ASIC synthesis and verification.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Challenges and opportunities for low power FPGAs in nanometer technologies.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Improving the efficiency of static timing analysis with false paths.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Coping With Uncertainty in FPGA Architecture Design.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005


Efficient static timing analysis and applications using edge masks.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Advances and trends in FPGA design.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Architecture and CAD for FPGAs.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Improving FPGA Performance and Area Using an Adaptive Logic Module.
Proceedings of the Field Programmable Logic and Application, 2004

MAX II: A low-cost, high-performance LUT-based CPLD.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002
Automatic generation of synthetic sequential benchmark circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Interconnect enhancements for a high-speed PLD architecture.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001
Interconnect prediction for programmable logic devices.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

1999
Applications of clone circuits to issues in physical-design.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Equivalence classes of clone circuits for physical-design benchmarking.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Characterization and parameterized generation of synthetic combinational benchmark circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

1997
Generation of Synthetic Sequential Benchmark Circuits.
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1996
Upward Planning of Single-Source Acyclic Digraphs.
SIAM J. Comput., 1996

Characterization and Parameterized Random Generation of Digital Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

1991
Upward Planar Drawing of Single Source Acyclic Digraphs.
Proceedings of the Second Annual ACM/SIGACT-SIAM Symposium on Discrete Algorithms, 1991


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