Cristian Sestito
Orcid: 0000-0002-7731-0002
According to our database1,
Cristian Sestito
authored at least 13 papers
between 2020 and 2025.
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Bibliography
2025
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025
3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads.
CoRR, February, 2025
L-Sort: On-Chip Spike Sorting With Efficient Median-of-Median Detection and Localization-Based Clustering.
IEEE Open J. Circuits Syst., 2025
Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks - Part II: Architecture and Hardware Implementation.
CoRR, 2024
TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks - Part I: Dataflow and Analytical Modelling.
CoRR, 2024
PyT-NeuroPack: A Hybrid PyTorch/Memristor-Crossbar Simulation Tool for Convolutional Neural Networks.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024
2023
J. Signal Process. Syst., October, 2023
2022
Proceedings of the International Joint Conference on Neural Networks, 2022
Design-Space Exploration of Quantized Transposed Convolutional Neural Networks for FPGA-based Systems-on-Chip.
Proceedings of the IEEE Intl. Conf. on Dependable, 2022
2021
Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions.
J. Imaging, 2021
2020
J. Imaging, 2020
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020