Pasquale Corsonello

Orcid: 0000-0002-9528-1110

Affiliations:
  • University of Calabria, Cosenza, Italy


According to our database1, Pasquale Corsonello authored at least 114 papers between 1998 and 2024.

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Bibliography

2024
Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs.
J. Supercomput., July, 2024

An explainable embedded neural system for on-board ship detection from optical satellite imagery.
Eng. Appl. Artif. Intell., 2024

2023
Design of Leading Zero Counters on FPGAs.
IEEE Embed. Syst. Lett., September, 2023

A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Design of Approximate Bilateral Filters for Image Denoising on FPGAs.
IEEE Access, 2023

Abnormal ECG Detection in Wearable Devices Using Compressed Learning.
Proceedings of the IEEE International Conference on Networking, Sensing and Control, 2023

Secure and Energy-Efficient ECG Signal Monitoring in the IoT Healthcare using Compressive Sensing.
Proceedings of the IEEE Intl Conf on Dependable, 2023

2022
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes.
Sensors, 2022

Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems.
IEEE Access, 2022

Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video Processing on FPGA.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Heterogeneous FPGA-based System for Real-Time Drowsiness Detection.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

ERMES: Efficient Racetrack Memory Emulation System based on FPGA.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation.
IEEE Trans. Circuits Syst., 2020

Stereo vision architecture for heterogeneous systems-on-chip.
J. Real Time Image Process., 2020

Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip.
J. Imaging, 2020

Design of a real-time face detection architecture for heterogeneous systems-on-chips.
Integr., 2020

Parallel architecture of power-of-two multipliers for FPGAs.
IET Circuits Devices Syst., 2020

Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis.
Sensors, 2019

Multimodal background subtraction for high-performance embedded systems.
J. Real Time Image Process., 2019

Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018
Design of Real-Time FPGA-based Embedded System for Stereo Vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Designing Fast Convolutional Engines for Deep Learning Applications.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
An efficient hardware-oriented stereo matching algorithm.
Microprocess. Microsystems, 2016

Design of efficient QCA multiplexers.
Int. J. Circuit Theory Appl., 2016

2015
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Power supply noise in accurate delay model for the sub-threshold domain.
Integr., 2015

A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity.
Int. J. Circuit Theory Appl., 2015

Novel Varactor-Loaded Phasing Line for Reflectarray Unit Cell with Large Reconfigurability Frequency Range.
Proceedings of the New Contributions in Information Systems and Technologies, 2015

Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Area-Delay Efficient Binary Adders in QCA.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.
Int. J. Circuit Theory Appl., 2014

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations.
Int. J. Circuit Theory Appl., 2014

Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates.
Int. J. Circuit Theory Appl., 2014

A novel background subtraction method based on color invariants and grayscale levels.
Proceedings of the International Carnahan Conference on Security Technology, 2014

2013
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm.
Comput. Vis. Image Underst., 2013

2012
Low-Power Level Shifter for Multi-Supply Voltage Designs.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Analytical Delay Model Considering Variability Effects in Subthreshold Domain.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Comparative analysis of yield optimized pulsed flip-flops.
Microelectron. Reliab., 2012

Low-cost FPGA stereo vision system for real time disparity maps calculation.
Microprocess. Microsystems, 2012

Energy-efficient single-clock-cycle binary comparator.
Int. J. Circuit Theory Appl., 2012

2011
Tapered-Vth Approach for Energy-Efficient CMOS Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference.
IEEE J. Solid State Circuits, 2011

Fast-squarer circuits using 3-bit-scan without overlapping bits.
Int. J. Circuit Theory Appl., 2011

Efficient memory architecture for image processing.
Int. J. Circuit Theory Appl., 2011

Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications.
ACM Trans. Reconfigurable Technol. Syst., 2010

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A new low-power high-speed single-clock-cycle binary comparator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A Low-Leakage Single-Ended 6T SRAM Cell.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

Impact of Random Process Variations on Different 65nm SRAM Cell Topologies.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

2009
Designing High-Speed Adders in Power-Constrained Environments.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron., 2009

Low-power split-path data-driven dynamic logic.
IET Circuits Devices Syst., 2009

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems.
Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, 2009

New performance/power/area efficient, reliable full adder design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals.
Microprocess. Microsystems, 2008

A matrix product accelerator for field programmable systems on chip.
Microprocess. Microsystems, 2008

High-performance noise-tolerant circuit techniques for CMOS dynamic logic.
IET Circuits Devices Syst., 2008

Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
VLSI implementations of efficient isotropic flexible 2D convolvers.
IET Circuits Devices Syst., 2007

MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing.
Proceedings of the Embedded Computer Systems: Architectures, 2007

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Design and Implementation of a 90nm Low bit-rate Image Compression Core.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Low bit rate image compression core for onboard space applications.
IEEE Trans. Circuits Syst. Video Technol., 2006

Simd Multipliers for Accelerating Embedded Processors in FPGAS.
J. Circuits Syst. Comput., 2006

Leakage energy reduction techniques in deep submicron cache memories: a comparative study.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An integrated countermeasure against differential power analysis for secure smart-cards.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

SAD-Based Stereo Matching Circuit for FPGAs.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Efficient Addition Circuits for Modular Design of Processors-in-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A high-performance fully reconfigurable FPGA-based 2D convolution processor.
Microprocess. Microsystems, 2005

Microprocessor-based FPGA implementation of SPIHT image compression subsystems.
Microprocess. Microsystems, 2005

Efficient Reconfigurable Manchester Adders for Low-power Media Processing.
J. Circuits Syst. Comput., 2005

Fast Low-Power 64-Bit Modular Hybrid Adder.
Proceedings of the Integrated Circuit and System Design, 2005

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Variable precision arithmetic circuits for FPGA-based multimedia processors.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Area- and Power-Reduced Standard-Cell Spanning Tree Adders.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
A high-speed energy-efficient 64-bit reconfigurable binary adder.
IEEE Trans. Very Large Scale Integr. Syst., 2003

A low-power sub-nanosecond standard-cells based adder.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
VLSI circuits for low-power high-speed asynchronous addition.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

Speed-efficient wide adders for VIRTEX FPGAs.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Dynamic power of CMOS gates driving lossy transmission lines.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Area-time-power tradeoff in cellular arrays VLSI implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2000

VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.
Proceedings of the Integrated Circuit Design, 2000

Designing High-Speed Asynchronous Pipelines.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
A 56-bit self-timed adder for high speed asynchronous datapath.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
High performance VLSI modules for division and square root.
Microprocess. Microsystems, 1998


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