Dai Yamamoto

According to our database, Dai Yamamoto authored at least 27 papers between 2005 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

A Chameleon Hash-based Method for Proving Execution of Business Processes.

Tadanobu Tsunoda, Kazuaki Nimura, Dai Yamamoto, Kouichi Yasaki, Rikuhiro Kojima, Yosuke Nakamura

J. Inf. Process., 2022

2021

Novel Deception Techniques for Malware Detection on Industrial Control Systems.

Takanori Machida, Dai Yamamoto, Yuki Unno, Hisashi Kojima

J. Inf. Process., 2021

A New Schnorr Multi-Signatures to Support Both Multiple Messages Signing and Key Aggregation.

Rikuhiro Kojima, Dai Yamamoto, Takeshi Shimoyama, Kouichi Yasaki, Kazuaki Nimura

J. Inf. Process., 2021

2020

A Novel Scheme of Schnorr Multi-signatures for Multiple Messages with Key Aggregation.

Rikuhiro Kojima, Dai Yamamoto, Takeshi Shimoyama, Kouichi Yasaki, Kazuaki Nimura

Proceedings of the Advances on Broad-Band Wireless Computing, Communication and Applications, 2020

2018

A Secure Framework for User-Key Provisioning to SGX Enclaves.

Takanori Machida, Dai Yamamoto, Ikuya Morikawa, Hirotaka Kokubo, Hisashi Kojima

Proceedings of the Advances in Network-Based Information Systems, 2018

2016

Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks.

Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

ASIC implementation of random number generators using SR latches and its evaluation.

Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto

EURASIP J. Inf. Secur., 2016

Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs.

Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.

Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto

Proceedings of the 6th International Workshop on Trustworthy Embedded Devices, 2016

2015

A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs.

Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, Naoya Torii

J. Cryptogr. Eng., 2015

Implementation of double arbiter PUF and its performance evaluation on FPGA.

Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Dynamic Behavior of RS latches using FIB processing and probe connection.

Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto

IACR Cryptol. ePrint Arch., 2014

A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering.

Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii

Proceedings of the Advances in Information and Computer Security, 2014

Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis.

Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii

Proceedings of the 2014 Federated Conference on Computer Science and Information Systems, 2014

A New Mode of Operation for Arbiter PUF to Improve Uniqueness on FPGA.

Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama

Proceedings of the 2014 Federated Conference on Computer Science and Information Systems, 2014

2013

Variety enhancement of PUF responses using the locations of random outputting RS latches.

Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh

J. Cryptogr. Eng., 2013

Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches.

Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii

Proceedings of the Smart Card Research and Advanced Applications, 2013

2012

Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs.

Dai Yamamoto, Gabriel Hospodar, Roel Maes, Ingrid Verbauwhede

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2012

2011

Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher.

Dai Yamamoto, Kouichi Itoh, Jun Yajima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches.

Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Takao Ochiai, Masahiko Takenaka, Kouichi Itoh

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010

Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher.

Dai Yamamoto, Jun Yajima, Kouichi Itoh

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Very Compact Hardware Implementation of the KASUMI Block Cipher.

Dai Yamamoto, Kouichi Itoh, Jun Yajima

Proceedings of the Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices, 2010

2009

Collision-Based Power Attack for RSA with Small Public Exponent.

Kouichi Itoh, Dai Yamamoto, Jun Yajima, Wakaha Ogata

IEICE Trans. Inf. Syst., 2009

2008

Design and Experimental Evaluation of a Scheme for Maximal Improvement of End-to-End QoS in Heterogeneous IP Networks.

Dai Yamamoto, Hideki Tode, Toshihiro Masaki, Koso Murakami

IEICE Trans. Commun., 2008

A Very Compact Hardware Implementation of the MISTY1 Block Cipher.

Dai Yamamoto, Jun Yajima, Kouichi Itoh

Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

2007

Design and Empirical Evaluation of Control Scheme for End-to-End Delay Stabilization and Packet Loss Improvement in Broadband IP Network.

Dai Yamamoto, Hideki Tode, Toshihiro Masaki, Koso Murakami

Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

2005

A Method for Guaranteeing End-to-End Delay by Mutual Cooperation between IP Routers.

Dai Yamamoto, Rie Fujita, Hideki Tode, Koso Murakami, Toshihiro Masaki

Proceedings of the 30th Annual IEEE Conference on Local Computer Networks (LCN 2005), 2005