Ingrid Verbauwhede

According to our database1, Ingrid Verbauwhede authored at least 384 papers between 1987 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to design of secure integrated circuits and systems".

Timeline

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Bibliography

2019
Compact and Flexible FPGA Implementation of Ed25519 and X25519.
ACM Trans. Embedded Comput. Syst., 2019

Atlas: Application Confidentiality in Compromised Embedded Systems.
IEEE Trans. Dependable Sec. Comput., 2019

Hardware-Efficient Post-Processing Architectures for True Random Number Generators.
IEEE Trans. on Circuits and Systems, 2019

Single-Round Pattern Matching Key Generation Using Physically Unclonable Function.
Security and Communication Networks, 2019

FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data.
IACR Cryptology ePrint Archive, 2019

Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on Falcon.
IACR Cryptology ePrint Archive, 2019

Timing attacks on Error Correcting Codes in Post-Quantum Secure Schemes.
IACR Cryptology ePrint Archive, 2019

Advanced profiling for probabilistic Prime+Probe attacks and covert channels in ScatterCache.
CoRR, 2019

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

The Impact of Error Dependencies on Ring/Mod-LWE/LWR Based Schemes.
Proceedings of the Post-Quantum Cryptography - 10th International Conference, 2019

Decryption Failure Attacks on IND-CCA Secure Lattice-Based Schemes.
Proceedings of the Public-Key Cryptography - PKC 2019, 2019

FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on the Falcon signature scheme.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Design Principles for True Random Number Generators for Security Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Private Mobile Pay-TV From Priced Oblivious Transfer.
IEEE Trans. Information Forensics and Security, 2018

Saber on ARM CCA-secure module lattice-based key encapsulation on ARM.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

A Cautionary Note When Looking for a Truly Reconfigurable Resistive RAM PUF.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation.
IEEE Trans. Computers, 2018

Hardware-Based Trusted Computing Architectures for Isolation and Attestation.
IEEE Trans. Computers, 2018

Constant-Time Discrete Gaussian Sampling.
IEEE Trans. Computers, 2018

Arithmetic of $$\tau $$ τ -adic expansions for lightweight Koblitz curve cryptography.
J. Cryptographic Engineering, 2018

Saber on ARM CCA-secure module lattice-based key encapsulation on ARM.
IACR Cryptology ePrint Archive, 2018

The impact of error dependencies on Ring/Mod-LWE/LWR based schemes.
IACR Cryptology ePrint Archive, 2018

On the impact of decryption failures on the security of LWE/LWR based schemes.
IACR Cryptology ePrint Archive, 2018

EE2: Workshop on circuits for social good.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

F1: Intelligent energy-efficient systems at the edge of IoT.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Closer Look at the Delay-Chain based TRNG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A multi-bit/cell PUF using analog breakdown positions in CMOS.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

The Impact of Pulsed Electromagnetic Fault Injection on True Random Number Generators.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

Teaching HW/SW codesign with a Zynq ARM/FPGA SoC.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

Design and testing methodologies for true random number generators towards industry certification.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Towards inter-vendor compatibility of true random number generators for FPGAs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards Efficient and Automated Side Channel Evaluations at Design Time.
Proceedings of the PROOFS 2018, 2018

An In-Depth and Black-Box Characterization of the Effects of Laser Pulses on ATmega328P.
Proceedings of the Smart Card Research and Advanced Applications, 2018

A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Sancus 2.0: A Low-Cost Security Architecture for IoT Devices.
ACM Trans. Priv. Secur., 2017

High-Performance Ideal Lattice-Based Cryptography on 8-Bit AVR Microcontrollers.
ACM Trans. Embedded Comput. Syst., 2017

LiBrA-CAN: Lightweight Broadcast Authentication for Controller Area Networks.
ACM Trans. Embedded Comput. Syst., 2017

Hardware Assisted Fully Homomorphic Function Evaluation and Encrypted Search.
IEEE Trans. Computers, 2017

Elliptic Curve Cryptography with Efficiently Computable Endomorphisms and Its Hardware Implementations for the Internet of Things.
IEEE Trans. Computers, 2017

A 5.1μJ per point-multiplication elliptic curve cryptographic processor.
I. J. Circuit Theory and Applications, 2017

Fast Leakage Assessment.
IACR Cryptology ePrint Archive, 2017

Lightweight Prediction-Based Tests for On-Line Min-Entropy Estimation.
Embedded Systems Letters, 2017

A survey of Hardware-based Control Flow Integrity (CFI).
CoRR, 2017

SOFIA: Software and control flow integrity architecture.
Computers & Security, 2017

STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

The Monte Carlo PUF.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Dude, is my code constant time?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Fast Leakage Assessment.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2017, 2017

SCM: Secure Code Memory Architecture.
Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security, 2017

Fault Analysis of the ChaCha and Salsa Families of Stream Ciphers.
Proceedings of the Smart Card Research and Advanced Applications, 2017

On-chip jitter measurement for true random number generators.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
A Lockdown Technique to Prevent Machine Learning on PUFs for Lightweight Authentication.
IEEE Trans. Multi-Scale Computing Systems, 2016

Masking ring-LWE.
J. Cryptographic Engineering, 2016

Providing security on demand using invasive computing.
it - Information Technology, 2016

Canary Numbers: Design for Light-weight Online Testability of True Random Number Generators.
IACR Cryptology ePrint Archive, 2016

Dude, is my code constant time?
IACR Cryptology ePrint Archive, 2016

Efficient Finite field multiplication for isogeny based post quantum cryptography.
IACR Cryptology ePrint Archive, 2016

Efficient Finite Field Multiplication for Isogeny Based Post Quantum Cryptography.
Proceedings of the Arithmetic of Finite Fields - 6th International Workshop, 2016

Embedded Security.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A Tiny Coprocessor for Elliptic Curve Cryptography over the 256-bit NIST Prime Field.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Ring-LWE: Applications to Cryptography and Their Efficient Realization.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Hold Your Breath, PRIMATEs Are Lightweight.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016

Additively Homomorphic Ring-LWE Masking.
Proceedings of the Post-Quantum Cryptography - 7th International Workshop, 2016

Binary decision diagram to design balanced secure logic styles.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Iterating Von Neumann's post-processing under hardware constraints.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Upper bounds on the min-entropy of RO Sum, Arbiter, Feed-Forward Arbiter, and S-ArbRO PUFs.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

VLSI Design Methods for Low Power Embedded Encryption.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Hardware acceleration of a software-based VPN.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016


Software security: Vulnerabilities and countermeasures for two attacker models.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

SOFIA: Software and control flow integrity architecture.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Design and Implementation of a Waveform-Matching Based Triggering System.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2016

On the Feasibility of Cryptography for a Wireless Insulin Pump System.
Proceedings of the Sixth ACM on Conference on Data and Application Security and Privacy, 2016

Efficient Fuzzy Extraction of PUF-Induced Secrets: Theory and Applications.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2016, 2016

A Fast and Compact FPGA Implementation of Elliptic Curve Cryptography Using Lambda Coordinates.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2016, 2016

2015
Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms.
IEEE Trans. VLSI Syst., 2015

Secure, Remote, Dynamic Reconfiguration of FPGAs.
TRETS, 2015

Anonymous Split E-Cash - Toward Mobile Anonymous Payments.
ACM Trans. Embedded Comput. Syst., 2015

High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems.
IEEE Trans. on Circuits and Systems, 2015

Helper Data Algorithms for PUF-Based Key Generation: Overview and Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs.
J. Cryptographic Engineering, 2015

The Energy Budget for Wireless Security: Extended Version.
IACR Cryptology ePrint Archive, 2015

Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation.
IACR Cryptology ePrint Archive, 2015

Lightweight Coprocessor for Koblitz Curves: 283-bit ECC Including Scalar Conversion with only 4300 Gates.
IACR Cryptology ePrint Archive, 2015

A masked ring-LWE implementation.
IACR Cryptology ePrint Archive, 2015

Consolidating masking schemes.
IACR Cryptology ePrint Archive, 2015

Single-Cycle Implementations of Block Ciphers.
IACR Cryptology ePrint Archive, 2015

A New Model for Error-Tolerant Side-Channel Cube Attacks.
IACR Cryptology ePrint Archive, 2015

On the Implementation of Unified Arithmetic on Binary Huff Curves.
IACR Cryptology ePrint Archive, 2015

Secure Sketch Metamorphosis: Tight Unified Bounds.
IACR Cryptology ePrint Archive, 2015

DPA, Bitslicing and Masking at 1 GHz.
IACR Cryptology ePrint Archive, 2015

VLSI Implementation of Double-Base Scalar Multiplication on a Twisted Edwards Curve with an Efficiently Computable Endomorphism.
IACR Cryptology ePrint Archive, 2015

Efficient Ring-LWE Encryption on 8-bit AVR Processors.
IACR Cryptology ePrint Archive, 2015

A Survey on Lightweight Entity Authentication with Strong PUFs.
ACM Comput. Surv., 2015

RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms.
SCIENCE CHINA Information Sciences, 2015

Single-Cycle Implementations of Block Ciphers.
Proceedings of the Lightweight Cryptography for Security and Privacy, 2015

24.1 Circuit challenges from cryptography.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

On-the-fly tests for non-ideal true random number generators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Embedded HW/SW platform for on-the-fly testing of true random number generators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Efficient software implementation of ring-LWE encryption.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Highly efficient entropy extraction for true random number generators on FPGAs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Consolidating Masking Schemes.
Proceedings of the Advances in Cryptology - CRYPTO 2015, 2015

Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

Lightweight Coprocessor for Koblitz Curves: 283-Bit ECC Including Scalar Conversion with only 4300 Gates.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

A Masked Ring-LWE Implementation.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

DPA, Bitslicing and Masking at 1 GHz.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

Efficient Ring-LWE Encryption on 8-Bit AVR Processors.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

Soteria: Offline Software Protection within Low-cost Embedded Devices.
Proceedings of the 31st Annual Computer Security Applications Conference, 2015

2014
Test Versus Security: Past and Present.
IEEE Trans. Emerging Topics Comput., 2014

Fault Injection Modeling Attacks on 65 nm Arbiter and RO Sum PUFs via Environmental Changes.
IEEE Trans. on Circuits and Systems, 2014

Novel RNS Parameter Selection for Fast Modular Multiplication.
IEEE Trans. Computers, 2014

BLAKE-512-Based 128-Bit CCA2 Secure Timing Attack Resistant McEliece Cryptoprocessor.
IEEE Trans. Computers, 2014

Design Methods for Secure Hardware (NII Shonan Meeting 2014-11).
NII Shonan Meet. Rep., 2014

RECTANGLE: A Bit-slice Ultra-Lightweight Block Cipher Suitable for Multiple Platforms.
IACR Cryptology ePrint Archive, 2014

Compact and Side Channel Secure Discrete Gaussian Sampling.
IACR Cryptology ePrint Archive, 2014

Chaskey: An Efficient MAC Algorithm for 32-bit Microcontrollers.
IACR Cryptology ePrint Archive, 2014

Secure Lightweight Entity Authentication with Strong PUFs: Mission Impossible II.
IACR Cryptology ePrint Archive, 2014

Secure Mutual Testing Strategy for Cryptographic SoCs.
IACR Cryptology ePrint Archive, 2014

Efficient Software Implementation of Ring-LWE Encryption.
IACR Cryptology ePrint Archive, 2014

High-speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems.
IACR Cryptology ePrint Archive, 2014

Chaskey: An Efficient MAC Algorithm for 32-bit Microcontrollers.
Proceedings of the Selected Areas in Cryptography - SAC 2014, 2014

A noise bifurcation architecture for linear additive physical functions.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Key-recovery attacks on various RO PUF constructions via helper data manipulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Software Only, Extremely Compact, Keccak-based Secure PRNG on ARM Cortex-M.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Ultra Low-Power implementation of ECC on the ARM Cortex-M0+.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Attacking PUF-Based Pattern Matching Key Generators via Helper Data Manipulation.
Proceedings of the Topics in Cryptology - CT-RSA 2014, 2014

Generic DPA Attacks: Curse or Blessing?
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014

A Note on the Use of Margins to Compare Distinguishers.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014

Compact Ring-LWE Cryptoprocessor.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

Secure Lightweight Entity Authentication with Strong PUFs: Mission Impossible?
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

How to Use Koblitz Curves on Small Devices?
Proceedings of the Smart Card Research and Advanced Applications, 2014

Secure interrupts on low-end microcontrollers.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Hardware Designer's Guide to Fault Attacks.
IEEE Trans. VLSI Syst., 2013

Teaching HW/SW Co-Design With a Public Key Cryptography Application.
IEEE Trans. Education, 2013

Security Analysis of Industrial Test Compression Schemes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

SPONGENT: The Design Space of Lightweight Cryptographic Hashing.
IEEE Trans. Computers, 2013

Compact Hardware Implementation of Ring-LWE Cryptosystems.
IACR Cryptology ePrint Archive, 2013

Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms.
IACR Cryptology ePrint Archive, 2013

Secure PRNG Seeding on Commercial Off-the-Shelf Microcontrollers.
IACR Cryptology ePrint Archive, 2013

Fault Injection Modeling Attacks on 65nm Arbiter and RO Sum PUFs via Environmental Changes.
IACR Cryptology ePrint Archive, 2013

Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation.
IACR Cryptology ePrint Archive, 2013

Attacking PUF-Based Pattern Matching Key Generators via Helper Data Manipulation.
IACR Cryptology ePrint Archive, 2013

Ultra Low-Power implementation of ECC on the ARM Cortex-M0+.
IACR Cryptology ePrint Archive, 2013

Dietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures.
IACR Cryptology ePrint Archive, 2013

Secure JTAG Implementation Using Schnorr Protocol.
J. Electronic Testing, 2013

Sancus: Low-cost Trustworthy Extensible Networked Devices with a Zero-software Trusted Computing Base.
Proceedings of the 22th USENIX Security Symposium, Washington, DC, USA, August 14-16, 2013, 2013

High Precision Discrete Gaussian Sampling on FPGAs.
Proceedings of the Selected Areas in Cryptography - SAC 2013, 2013

Dietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures.
Proceedings of the Radio Frequency Identification, 2013

A single-chip solution for the secure remote configuration of FPGAs using bitstream compression.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

The exponential impact of creativity in computer engineering education.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Protected Software Module Architectures.
Proceedings of the ISSE 2013, 2013

Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Low-energy encryption for medical devices: security adds an extra design dimension.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A New Model for Error-Tolerant Side-Channel Cube Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

On the Implementation of Unified Arithmetic on Binary Huff Curves.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

Inherent PUFs and secure PRNGs on commercial off-the-shelf microcontrollers.
Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

Secure PRNG seeding on commercial off-the-shelf microcontrollers.
Proceedings of the TrustED'13, 2013

2012
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates.
IEEE Trans. VLSI Syst., 2012

Guest Editorial Integrated Circuit and System Security.
IEEE Trans. Information Forensics and Security, 2012

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs.
IEEE Trans. Information Forensics and Security, 2012

Efficient Hardware Implementation of Fp-Arithmetic for Pairing-Friendly Curves.
IEEE Trans. Computers, 2012

Extending ECC-based RFID authentication protocols to privacy-preserving multi-party grouping proofs.
Personal and Ubiquitous Computing, 2012

A Practical Attack on KeeLoq.
J. Cryptology, 2012

Scan attacks on side-channel and fault attack resistant public-key implementations.
J. Cryptographic Engineering, 2012

PUFs: Myth, Fact or Busted? A Security Evaluation of Physically Unclonable Functions (PUFs) Cast in Silicon (Extended Version).
IACR Cryptology ePrint Archive, 2012

Efficient and secure hardware.
Datenschutz und Datensicherheit, 2012

Three Phase Dynamic Current Mode Logic: A More Secure DyCML to Achieve a More Balanced Power Consumption.
Proceedings of the Information Security Applications - 13th International Workshop, 2012

Machine learning attacks on 65nm Arbiter PUFs: Accurate modeling poses strict bounds on usability.
Proceedings of the 2012 IEEE International Workshop on Information Forensics and Security, 2012

Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2012

Faster Pairing Coprocessor Architecture.
Proceedings of the Pairing-Based Cryptography - Pairing 2012, 2012

Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform.
Proceedings of the Pairing-Based Cryptography - Pairing 2012, 2012

Tiny application-specific programmable processor for BCH decoding.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Design solutions for securing SRAM cell against power analysis.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

A systematic M safe-error detection in hardware implementations of cryptographic algorithms.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Reverse Fuzzy Extractors: Enabling Lightweight Mutual Authentication for PUF-Enabled RFIDs.
Proceedings of the Financial Cryptography and Data Security, 2012

Experimental evaluation of Physically Unclonable Functions in 65 nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Low-cost implementations of on-the-fly tests for random number generators.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

PUF-based secure test wrapper design for cryptographic SoC testing.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Power Analysis of Atmel CryptoMemory - Recovering Keys from Secure EEPROMs.
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012

A New Scan Attack on RSA in Presence of Industrial Countermeasures.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

Selecting Time Samples for Multivariate DPA Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

PUFs: Myth, Fact or Busted? A Security Evaluation of Physically Unclonable Functions (PUFs) Cast in Silicon.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

LiBrA-CAN: A Lightweight Broadcast Authentication Protocol for Controller Area Networks.
Proceedings of the Cryptology and Network Security, 11th International Conference, 2012

An Updated Survey on Secure ECC Implementations: Attacks, Countermeasures and Cost.
Proceedings of the Cryptography and Security: From Theory to Applications, 2012

Theory and Practice of a Leakage Resilient Masking Scheme.
Proceedings of the Advances in Cryptology - ASIACRYPT 2012, 2012

Interface Design for Mapping a Variety of RSA Exponentiation Algorithms on a HW/SW Co-design Platform.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

A Speed Area Optimized Embedded Co-processor for McEliece Cryptosystem.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Constructing Application-Specific Memory Hierarchies on FPGAs.
Trans. HiPEAC, 2011

Machine learning in side-channel analysis: a first study.
J. Cryptographic Engineering, 2011

Tripartite modular multiplication.
Integration, 2011

Design and design methods for unified multiplier and inverter and its application for HECC.
Integration, 2011

A High Speed Pairing Coprocessor Using RNS and Lazy Reduction.
IACR Cryptology ePrint Archive, 2011

SPONGENT: The Design Space of Lightweight Cryptographic Hashing.
IACR Cryptology ePrint Archive, 2011

The communication and computation cost of wireless security: extended abstract.
Proceedings of the Fourth ACM Conference on Wireless Network Security, 2011

Hierarchical ECC-Based RFID Authentication Protocol.
Proceedings of the RFID. Security and Privacy - 7th International Workshop, 2011

Secure remote reconfiguration of an FPGA-based embedded system.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

The cost of cryptography: Is low budget possible?
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Systematic security evaluation method against C safe-error attacks.
Proceedings of the HOST 2011, 2011

Physically unclonable functions: manufacturing variability as an unclonable device identifier.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

The Fault Attack Jungle - A Classification Model to Guide You.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

Low-cost fault detection method for ECC using Montgomery powering ladder.
Proceedings of the Design, Automation and Test in Europe, 2011

FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

spongent: A Lightweight Hash Function.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010
Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions.
Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010

Anti-counterfeiting, Untraceability and Other Security Challenges for RFID Systems: Public-Key-Based Protocols and Hardware.
Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010

Faster Interleaved Modular Multiplication Based on Barrett and Montgomery Reduction Methods.
IEEE Trans. Computers, 2010

Low-cost untraceable authentication protocols for RFID.
Proceedings of the Third ACM Conference on Wireless Network Security, 2010

Speeding Up Bipartite Modular Multiplication.
Proceedings of the Arithmetic of Finite Fields, Third International Workshop, 2010

PrETP: Privacy-Preserving Electronic Toll Pricing.
Proceedings of the 19th USENIX Security Symposium, 2010

Wide-Weak Privacy-Preserving RFID Authentication Protocols.
Proceedings of the Mobile Lightweight Wireless Systems, 2010

Privacy-Preserving ECC-Based Grouping Proofs for RFID.
Proceedings of the Information Security - 13th International Conference, 2010

Prototyping Platform for Performance Evaluation of SHA-3 Candidates.
Proceedings of the HOST 2010, 2010

State-of-the-art of Secure ECC Implementations: A Survey on Known Side-channel Attacks and Countermeasures.
Proceedings of the HOST 2010, 2010

Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Low Cost Built in Self Test for Public Key Crypto Cores.
Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010

A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite Fields.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

An embedded platform for privacy-friendly road charging applications.
Proceedings of the Design, Automation and Test in Europe, 2010

Secure remote reconfiguration of FPGAs.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

10281 Summary - Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

10281 Abstracts Collection - Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

Revisiting Higher-Order DPA Attacks: .
Proceedings of the Topics in Cryptology, 2010

A compact FPGA-based architecture for elliptic curve cryptography over prime fields.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Implementation of binary edwards curves for very-constrained devices.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Hardware design for Hash functions.
Proceedings of the Secure Integrated Circuits and Systems, 2010

Compact Public-Key Implementations for RFID and Sensor Nodes.
Proceedings of the Secure Integrated Circuits and Systems, 2010

Signal Processing for Cryptography and Security Applications.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Practical DPA Attacks on MDPL.
IACR Cryptology ePrint Archive, 2009

Revisiting Higher-Order DPA Attacks: Multivariate Mutual Information Analysis.
IACR Cryptology ePrint Archive, 2009

Efficient implementation of anonymous credentials on Java Card smart cards.
Proceedings of the First IEEE International Workshop on Information Forensics and Security, 2009

Practical DPA attacks on MDPL.
Proceedings of the First IEEE International Workshop on Information Forensics and Security, 2009

Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors.
Proceedings of the 30th IEEE Symposium on Security and Privacy (S&P 2009), 2009

Future of Assurance: Ensuring that a System is Trustworthy.
Proceedings of the ISSE 2009, 2009

A soft decision helper data algorithm for SRAM PUFs.
Proceedings of the IEEE International Symposium on Information Theory, 2009

Modular Reduction without Precomputational Phase.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Light-weight implementation options for curve-based cryptography: HECC is also ready for RFID.
Proceedings of the 4th International Conference for Internet Technology and Secured Transactions, 2009

Analysis and Design of Active IC Metering Schemes.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Random numbers generation: Investigation of narrowtransitions suppression on FPGA.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Case Study : A class E power amplifier for ISO-14443A.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

Faster -Arithmetic for Cryptographic Pairings on Barreto-Naehrig Curves.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

Hardware evaluation of the Luffa hash family.
Proceedings of the 4th Workshop on Embedded Systems Security, 2009

2008
Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class.
Signal Processing Systems, 2008

Demonstration of Uncoordinated Multiple Access in Optical Communications.
IEEE Trans. on Circuits and Systems, 2008

Elliptic-Curve-Based Security Processor for RFID.
IEEE Trans. Computers, 2008

A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems.
IEEE Trans. Computers, 2008

Elliptic curve cryptography on embedded multicore systems.
Design Autom. for Emb. Sys., 2008

Revisiting a combinatorial approach toward measuring anonymity.
Proceedings of the 2008 ACM Workshop on Privacy in the Electronic Society, 2008

On the Practical Performance of Rateless Codes.
Proceedings of the WINSYS 2008, 2008

Modular Reduction in GF(2n) without Pre-computational Phase.
Proceedings of the Arithmetic of Finite Fields, 2nd International Workshop, 2008

A digit-serial architecture for inversion and multiplication in GF(2M).
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

HECC Goes Embedded: An Area-Efficient Implementation of HECC.
Proceedings of the Selected Areas in Cryptography, 15th International Workshop, SAC 2008, 2008

Perfect Matching Disclosure Attacks.
Proceedings of the Privacy Enhancing Technologies, 2008

Partition vs. Comparison Side-Channel Distinguishers: An Empirical Evaluation of Statistical Tests for Univariate Side-Channel Attacks against Two Unprotected CMOS Devices.
Proceedings of the Information Security and Cryptology, 2008

Unified Digit-Serial Multiplier and Inverter in Finite Field GF(2m).
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Exploiting Hardware Performance Counters.
Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

FPGA Design for Algebraic Tori-Based Public-Key Cryptography.
Proceedings of the Design, Automation and Test in Europe, 2008

Fault Analysis Study of IDEA.
Proceedings of the Topics in Cryptology, 2008

Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

On the high-throughput implementation of RIPEMD-160 hash algorithm.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Low-cost implementations of NTRU for pervasive security.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Cryptodinges - Geheime geschriften en raadsels ontcijferd.
Lannoo, ISBN: 978-90-209-7809-4, 2008

2007
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication.
IEEE Trans. VLSI Syst., 2007

Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n).
IEEE Trans. Computers, 2007

High-performance Public-key Cryptoprocessor for Wireless Mobile Applications.
MONET, 2007

HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor.
Integration, 2007

Transforming Signal Processing Applications into Parallel Implementations.
EURASIP J. Adv. Sig. Proc., 2007

A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
CoRR, 2007

Design Method for Constant Power Consumption of Differential Logic Circuits
CoRR, 2007

Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip
CoRR, 2007

HW/SW co-design for public-key cryptosystems on the 8051 micro-controller.
Computers & Electrical Engineering, 2007

Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems.
Computers & Electrical Engineering, 2007

A Compact Architecture for Montgomery Elliptic Curve Scalar Multiplication Processor.
Proceedings of the Information Security Applications, 8th International Workshop, 2007

Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations.
Proceedings of the Information Security Applications, 8th International Workshop, 2007

Montgomery Modular Multiplication Algorithm on Multi-Core Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Public-Key Cryptography for RFID-Tags.
Proceedings of the Fifth Annual IEEE International Conference on Pervasive Computing and Communications, 2007

Public-Key Cryptography on the Top of a Needle.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Secure IRIS Verification.
Proceedings of the IEEE International Conference on Acoustics, 2007

Side-channel resistant system-level design flow for public-key cryptography.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Efficient pipelining for modular multiplication architectures in prime fields.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Design methods for security and trust.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
An interactive codesign environment for domain-specific coprocessors.
ACM Trans. Design Autom. Electr. Syst., 2006

A digital design flow for secure integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Multilevel Design Validation in a Secure Embedded System.
IEEE Trans. Computers, 2006

Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors.
IEEE Trans. Computers, 2006

Securing Embedded Systems.
IEEE Security & Privacy, 2006

An Elliptic Curve Processor Suitable For RFID-Tags.
IACR Cryptology ePrint Archive, 2006

Efficient and Secure Fingerprint Verification for Embedded Devices.
EURASIP J. Adv. Sig. Proc., 2006

A Component-Based Design Environment for ESL Design.
IEEE Design & Test of Computers, 2006

Side-Channel Leakage Tolerant Architectures.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Trellis Codes with Low Ones Density for the OR Multiple Access Channel.
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006

A fast dual-field modular arithmetic logic unit and its hardware implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Flexible hardware architectures for curve-based cryptography.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Parallel Processing Hardware Architecture for Elliptic Curve Cryptosystems.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

FPGA Vendor Agnostic True Random Number Generator.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Low-Cost Elliptic Curve Cryptography for Wireless Sensor Networks.
Proceedings of the Security and Privacy in Ad-Hoc and Sensor Networks, 2006

Process Isolation for Reconfigurable Hardware.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Design with race-free hardware semantics.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Superscalar Coprocessor for High-Speed Curve-Based Cryptography.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

Throughput Optimized SHA-1 Architecture Using Unfolding Transformation.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

High Speed Channel Coding Architectures for the Uncoordinated OR Channel.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Skiing the embedded systems mountain.
ACM Trans. Embedded Comput. Syst., 2005

Platform-based design for an embedded-fingerprint-authentication device.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Integrated modelling and generation of a reconfigurable network-on-chip.
IJES, 2005

Extended abstract: a race-free hardware modeling language.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

Side-Channel Issues for Designing Secure Hardware Implementations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Automatic secure fingerprint verification system based on fuzzy vault scheme.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Multilevel design validation in a secure embedded system.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip.
Proceedings of the 2005 Design, 2005

A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs.
Proceedings of the 2005 Design, 2005

Design Method for Constant Power Consumption of Differential Logic Circuits.
Proceedings of the 2005 Design, 2005

Simulation models for side-channel information leaks.
Proceedings of the 42nd Design Automation Conference, 2005

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
Proceedings of the 42nd Design Automation Conference, 2005

Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design.
Proceedings of the 42nd Design Automation Conference, 2005

A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box.
Proceedings of the Topics in Cryptology, 2005

Microcoded coprocessor for embedded secure biometric authentication systems.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2n).
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Design of portable biometric authenticators - energy, performance, and security tradeoffs.
IEEE Trans. Consumer Electronics, 2004

High-Throughput Programmable Cryptocoprocessor.
IEEE Micro, 2004

Synthesis of Secure FPGA Implementations.
IACR Cryptology ePrint Archive, 2004

Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC's against Differential Power Analysis.
IACR Cryptology ePrint Archive, 2004

A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security IC's.
IACR Cryptology ePrint Archive, 2004

Architectural Design Features of a Programmable High Throughput AES Coprocessor.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Reducing radio energy consumption of key management protocols for wireless sensor networks.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Embedded Software Integration for Coarse-Grain Reconfigurable Systems.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Integrated Modeling and Generation of a Reconfigurable Network-on-Chip.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A realtime, memory efficient fingerprint verification system.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Secure Logic Synthesis.
Proceedings of the Field Programmable Logic and Application, 2004

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.
Proceedings of the 2004 Design, 2004

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation.
Proceedings of the 2004 Design, 2004

Interactive Cosimulation with Partial Evaluation.
Proceedings of the 2004 Design, 2004

A low power capacitive coupled bus interface based on pulsed signaling.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

The happy marriage of architecture and application in next-generation reconfigurable systems.
Proceedings of the First Conference on Computing Frontiers, 2004

Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques.
Proceedings of the 2004 International Conference on Compilers, 2004

Place and Route for Secure Standard Cell Design.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

Energy-Memory-Security Tradeoffs in Distributed Sensor Networks.
Proceedings of the Ad-Hoc, Mobile, and Wireless Networks: Third International Conference, 2004

2003
Domain-Specific Codesign for Embedded Security.
IEEE Computer, 2003

Teaching Trade-offs in System-level Design Methodologies.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Testing ThumbPod: Softcore bugs are hard to find.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system.
Proceedings of the 40th Design Automation Conference, 2003

Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

Finding the best system design flow for a high-speed JPEG encoder.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Guest editorial: low-power electronics and design.
IEEE Trans. VLSI Syst., 2002

Domain Specific Tools and Methods for Application in Security Processor Design.
Design Autom. for Emb. Sys., 2002

Reconfigurable interconnect for next generation systems.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Unlocking the design secrets of a 2.29 Gb/s Rijndael processor.
Proceedings of the 39th Design Automation Conference, 2002

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Proceedings of the 39th Design Automation Conference, 2002

A Security Protocol for Biometric Smart Cards.
Proceedings of the Fifth Smart Card Research and Advanced Application Conference, 2002

2001
Low power showdown: comparison of five DSP platforms implementing an LPC speech codec.
Proceedings of the IEEE International Conference on Acoustics, 2001

A Quick Safari Through the Reconfiguration Jungle.
Proceedings of the 38th Design Automation Conference, 2001

Panel: The Next HDL: If C++ is the Answer, What was the Question?
Proceedings of the 38th Design Automation Conference, 2001

Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2001

2000
Low power DSP's for wireless communications (embedded tutorial session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1998
A Low Power DSP Engine for Wireless Communications.
VLSI Signal Processing, 1998

1996
Analysis of multidimensional DSP specifications.
IEEE Trans. Signal Processing, 1996

1995
Synthesis for real time systems: Solutions and challenges.
VLSI Signal Processing, 1995

Guest editor's introduction design environments for DSP.
VLSI Signal Processing, 1995

1994
Specification and support for multidimensional DSP in the SILAGE language.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

Memory Estimation for High Level Synthesis.
Proceedings of the 31st Conference on Design Automation, 1994

1991
In-place memory management of algebraic algorithms on application specific ICs.
VLSI Signal Processing, 1991

1987
Security Considerations in the Design and Implementation of a new DES chip.
Proceedings of the Advances in Cryptology, 1987


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