Daichi Mukunoki

According to our database, Daichi Mukunoki authored at least 38 papers between 2010 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Layer-wise MoE Routing Locality under Shared-Prefix Code Generation: Token-Identity Decomposition and Compile-Equivalent Fork Redundancy.

Shun-ichiro Hayashi, Daichi Mukunoki, Tetsuya Hoshino, Takahiro Katagiri

CoRR, April, 2026

Improving HPC Code Generation Capability of LLMs via Online Reinforcement Learning with Real-Machine Benchmark Rewards.

Ryo Mikasa, Shun-ichiro Hayashi, Daichi Mukunoki, Tetsuya Hoshino, Takahiro Katagiri

CoRR, February, 2026

Learning-Augmented Performance Model for Tensor Product Factorization in High-Order FEM.

Xuanzhengbo Ren, Yuta Kawai, Tetsuya Hoshino, Hirofumi Tomita, Takahiro Katagiri, Daichi Mukunoki, Seiya Nishizawa

IEEE Access, 2026

DGEMM using FP64 Arithmetic Emulation and FP8 Tensor Cores with Ozaki Scheme.

Daichi Mukunoki

Proceedings of the Supercomputing Asia and International Conference on High Performance Computing in Asia Pacific Region Workshops, 2026

Evaluating Claude Code's Coding and Test Automation for GPU Acceleration ofa Legacy Fortran Application: A GeoFEM Case Study.

Tetsuya Hoshino, Shun-ichiro Hayashi, Daichi Mukunoki, Takahiro Katagiri, Toshihiro Hanawa

Proceedings of the Supercomputing Asia and International Conference on High Performance Computing in Asia Pacific Region Workshops, 2026

2025

3Dify: a Framework for Procedural 3D-CG Generation Assisted by LLMs Using MCP and RAG.

Shun-ichiro Hayashi, Daichi Mukunoki, Tetsuya Hoshino, Satoshi Ohshima, Takahiro Katagiri

CoRR, October, 2025

VibeCodeHPC: An Agent-Based Iterative Prompting Auto-Tuner for HPC Code Generation Using LLMs.

Shun-ichiro Hayashi, Koki Morita, Daichi Mukunoki, Tetsuya Hoshino, Takahiro Katagiri

CoRR, October, 2025

DGEMM without FP64 Arithmetic - Using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme.

Daichi Mukunoki

CoRR, August, 2025

Towards Generalized Parameter Tuning in Coherent Ising Machines: A Portfolio-Based Approach.

Tatsuro Hanyu, Takahiro Katagiri, Daichi Mukunoki, Tetsuya Hoshino

CoRR, July, 2025

Performance Evaluation of General Purpose Large Language Models for Basic Linear Algebra Subprograms Code Generation.

Daichi Mukunoki, Shun-ichiro Hayashi, Tetsuya Hoshino, Takahiro Katagiri

CoRR, July, 2025

Sparse Iterative Solvers Using High-Precision Arithmetic with Quasi Multi-Word Algorithms.

Daichi Mukunoki, Katsuhisa Ozaki

Proceedings of the 18th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2025

Performance Evaluation of Loop Body Splitting for Fast Modal Filtering in SCALE-DG on A64FX.

Xuanzhengbo Ren, Yuta Kawai, Hirofumi Tomita, Seiya Nishizawa, Takahiro Katagiri, Tetsuya Hoshino, Daichi Mukunoki, Masatoshi Kawai, Toru Nagai

Proceedings of the 2025 International Conference on High Performance Computing in Asia-Pacific Region Workshops, 2025

An Algorithm Portfolio Approach for Parameter Tuning in Coherent Ising Machines.

Tatsuro Hanyu, Takahiro Katagiri, Daichi Mukunoki, Tetsuya Hoshino

Proceedings of the Thirteenth International Symposium on Computing and Networking, CANDAR 2025, 2025

2024

Performance evaluation and modelling of single-precision matrix multiplication on Cerebras CS-2.

Ryunosuke Matsuzaki, Daichi Mukunoki, Takaaki Miyajima

Proceedings of the SC24-W: Workshops of the International Conference for High Performance Computing, 2024

Reduced-Precision and Reduced-Exponent Formats for Accelerating Adaptive Precision Sparse Matrix-Vector Product.

Stef Graillat, Fabienne Jézéquel, Théo Mary, Roméo Molina, Daichi Mukunoki

Proceedings of the Euro-Par 2024: Parallel Processing, 2024

2023

Sparse Matrix-Vector Multiplication with Reduced-Precision Memory Accessor.

Daichi Mukunoki, Masatoshi Kawai, Toshiyuki Imamura

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2022

Infinite-Precision Inner Product and Sparse Matrix-Vector Multiplication Using Ozaki Scheme with Dot2 on Manycore Processors.

Daichi Mukunoki, Katsuhisa Ozaki, Takeshi Ogita, Toshiyuki Imamura

Proceedings of the Parallel Processing and Applied Mathematics, 2022

2021

Task Scheduling Strategies for Batched Basic Linear Algebra Subprograms on Many-core CPUs.

Daichi Mukunoki, Yusuke Hirota, Toshiyuki Imamura

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Matrix Engines for High Performance Computing: A Paragon of Performance or Grasping at Straws?

Jens Domke, Emil Vatai, Aleksandr Drozd, Peng Chen, Yosuke Oyama, Lingqi Zhang, Shweta Salaria, Daichi Mukunoki, Artur Podobas, Mohamed Wahib, Satoshi Matsuoka

Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Accurate Matrix Multiplication on Binary128 Format Accelerated by Ozaki Scheme.

Daichi Mukunoki, Katsuhisa Ozaki, Takeshi Ogita, Toshiyuki Imamura

Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

A Rapid Euclidean Norm Calculation Algorithm that Reduces Overflow and Underflow.

Takeyuki Harayama, Shuhei Kudo, Daichi Mukunoki, Toshiyuki Imamura, Daisuke Takahashi

Proceedings of the Computational Science and Its Applications - ICCSA 2021, 2021

Conjugate Gradient Solvers with High Accuracy and Bit-wise Reproducibility between CPU and GPU using Ozaki scheme.

Daichi Mukunoki, Katsuhisa Ozaki, Takeshi Ogita, Roman Iakymchuk

Proceedings of the HPC Asia 2021: The International Conference on High Performance Computing in Asia-Pacific Region, 2021

2020

Performance and energy consumption of accurate and mixed-precision linear algebra kernels on GPUs.

Daichi Mukunoki, Takeshi Ogita

J. Comput. Appl. Math., 2020

White Paper from Workshop on Large-scale Parallel Numerical Computing Technology (LSPANC 2020): HPC and Computer Arithmetic toward Minimal-Precision Computing.

Roman Iakymchuk, Daichi Mukunoki, Artur Podobas, Fabienne Jézéquel, Toshiyuki Imamura, Norihisa Fujita, Jens Huthmann, Shuhei Kudo, Yiyu Tan, Jens Domke, Kai Torben Ohlhus, Takeshi Fukaya, Takeo Hoshi, Yuki Murakami, Maho Nakata, Takeshi Ogita, Kentaro Sano, Taisuke Boku

CoRR, 2020

Can We Avoid Rounding-Error Estimation in HPC Codes and Still Get Trustworthy Results?

Fabienne Jézéquel, Stef Graillat, Daichi Mukunoki, Toshiyuki Imamura, Roman Iakymchuk

Proceedings of the Software Verification - 12th International Conference, 2020

DGEMM Using Tensor Cores, and Its Accurate and Reproducible Versions.

Daichi Mukunoki, Katsuhisa Ozaki, Takeshi Ogita, Toshiyuki Imamura

Proceedings of the High Performance Computing - 35th International Conference, 2020

2019

Reproducible BLAS Routines with Tunable Accuracy Using Ozaki Scheme for Many-Core Architectures.

Daichi Mukunoki, Takeshi Ogita, Katsuhisa Ozaki

Proceedings of the Parallel Processing and Applied Mathematics, 2019

Design of an FPGA-Based Matrix Multiplier with Task Parallelism.

Yiyu Tan, Toshiyuki Imamura, Daichi Mukunoki

Proceedings of the Parallel Computing: Technology Trends, 2019

2018

Performance Analysis of 2D-compatible 2.5D-PDGEMM on Knights Landing Cluster.

Daichi Mukunoki, Toshiyuki Imamura

Proceedings of the Computational Science - ICCS 2018, 2018

2017

Implementation and Performance Analysis of 2.5D-PDGEMM on the K Computer.

Daichi Mukunoki, Toshiyuki Imamura

Proceedings of the Parallel Processing and Applied Mathematics, 2017

Design Towards Modern High Performance Numerical LA Library Enabling Heterogeneity and Flexible Data Formats.

Toshiyuki Imamura, Daichi Mukunoki, Yusuke Hirota, Susumu Yamada, Masahiko Machida

Proceedings of the Parallel Computing is Everywhere, 2017

2016

Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUs.

Daichi Mukunoki, Toshiyuki Imamura, Daisuke Takahashi

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Reduced-Precision Floating-Point Formats on GPUs for High Performance and Energy Efficient Computation.

Daichi Mukunoki, Toshiyuki Imamura

Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

2015

Fast Implementation of General Matrix-Vector Multiplication (GEMV) on Kepler GPUs.

Daichi Mukunoki, Toshiyuki Imamura, Daisuke Takahashi

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

2013

Using Quadruple Precision Arithmetic to Accelerate Krylov Subspace Methods on GPUs.

Daichi Mukunoki, Daisuke Takahashi

Proceedings of the Parallel Processing and Applied Mathematics, 2013

Optimization of Sparse Matrix-Vector Multiplication for CRS Format on NVIDIA Kepler Architecture GPUs.

Daichi Mukunoki, Daisuke Takahashi

Proceedings of the Computational Science and Its Applications - ICCSA 2013, 2013

2012

Implementation and Evaluation of Triple Precision BLAS Subroutines on GPUs.

Daichi Mukunoki, Daisuke Takahashi

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2010

Implementation and Evaluation of Quadruple Precision BLAS Functions on GPUs.

Daichi Mukunoki, Daisuke Takahashi

Proceedings of the Applied Parallel and Scientific Computing, 2010