Daijoon Hyun

Orcid: 0000-0002-0576-9666

According to our database1, Daijoon Hyun authored at least 23 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Bayesian Optimization for Parameter Tuning in Placement-Aware Logic Synthesis.
Proceedings of the 20th International SoC Design Conference, 2023

Interconnect Stack Parameter Optimization Using Genetic Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2021
Double Thresholding with Sine Entropy for Thermal Image Segmentation.
Traitement du Signal, 2021

Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Pedestrian Detection in Infrared Thermal Images Based on Raised Cosine Distribution.
Proceedings of the International SoC Design Conference, 2020

Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning.
ACM Trans. Design Autom. Electr. Syst., 2019

Integrated Approach of Airgap Insertion for Circuit Timing Optimization.
ACM Trans. Design Autom. Electr. Syst., 2019

Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Library Optimization for Near-Threshold Voltage Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Automatic insertion of airgap with design rule constraints.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Clock tree optimization through selective airgap insertion.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016
Buffer insertion to remove hold violations at multiple process corners.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Physical synthesis of DNA circuits with spatially localized gates.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015


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