Youngsoo Shin

Orcid: 0000-0002-7474-9212

According to our database1, Youngsoo Shin authored at least 165 papers between 1995 and 2024.

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Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to design tools for low power, high speed VLSI circuits and systems".

Timeline

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Bibliography

2024
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs.
IEEE Trans. Very Large Scale Integr. Syst., May, 2024

Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Too Many or Too Little: Investigating Different Decision-making Experiences of Maximizers and Satisficers in HCIs.
Proceedings of the 35th Australian Computer-Human Interaction Conference, 2023

Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

AI-EDA: Toward a Holistic Approach to AI-Powered EDA.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Block-Level Power Net Routing of Analog Circuit Using Reinforcement Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Lightning Talk 21: EDA with ML, Rule-Based, or Both?
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Fast Prediction of Dynamic IR-Drop Using Recurrent U-Net Architecture.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Supporting Users' Decision-Making Experiences through Hyper-Personalized Human-Technology Interactions.
Proceedings of the DIS '22: Designing Interactive Systems Conference, Virtual Event, Australia, June 13, 2022

2021
Computational Lithography Using Machine Learning Models.
IPSJ Trans. Syst. LSI Des. Methodol., 2021

Towards Designing Human-Centered Time Management Interfaces: The Development of 14 UX Design Guidelines for Time-related Experiences in Mobile HCI.
Proceedings of the MobileHCI '21: 23rd International Conference on Mobile Human-Computer Interaction, Extented Abstracts, Toulouse & Virtual Event, France, 27 September 2021, 2021

Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

PENCODER: Design for Prospective Memory and Older Adults.
Proceedings of the CHI '21: CHI Conference on Human Factors in Computing Systems, 2021

2020
Pre-layout clock tree estimation and optimization using artificial neural network.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Fast ECO Leakage Optimization Using Graph Convolutional Network.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning.
ACM Trans. Design Autom. Electr. Syst., 2019

Integrated Latch Placement and Cloning for Timing Optimization.
ACM Trans. Design Autom. Electr. Syst., 2019

Integrated Approach of Airgap Insertion for Circuit Timing Optimization.
ACM Trans. Design Autom. Electr. Syst., 2019

Neural Network Classifier-Based OPC With Imbalanced Training Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Endurance Enhancement of Multi-Level Cell Phase Change Memory.
Proceedings of the International Conference on Computer-Aided Design, 2019

Clock Gating Synthesis of Netlist with Cyclic Logic Paths.
Proceedings of the International Conference on Computer-Aided Design, 2019

Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops.
ACM Trans. Design Autom. Electr. Syst., 2018

Electrothermal Analysis With Nonconvective Boundary Conditions.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Memory-Efficient Parametric Semiglobal Matching.
IEEE Signal Process. Lett., 2018

Module grouping to reduce the area of test wrappers in SoCs.
Integr., 2018

Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).
IEEE Des. Test, 2018

Data-centered persuasion: Nudging user's prosocial behavior and designing social innovation.
Comput. Hum. Behav., 2018

Optimization of Machine Learning Guided Optical Proximity Correction.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Transient Clock Power Estimation of Pre-CTS Netlist.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Library Optimization for Near-Threshold Voltage Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Automatic insertion of airgap with design rule constraints.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Lithography Defect Probability and Its Application to Physical Design Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Design for experience innovation: understanding user experience in new product development.
Behav. Inf. Technol., 2017

Redundant Via insertion in SADP process with cut merging and optimization.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Clock tree optimization through selective airgap insertion.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Timing-aware wire width optimization for SADP process.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Cut mask optimization for multi-patterning directed self-assembly lithography.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization.
ACM Trans. Design Autom. Electr. Syst., 2016

Wakeup scheduling and its buffered tree synthesis for power gating circuits.
Integr., 2016

Area efficient neuromorphic circuit based on stochastic computation.
Proceedings of the International SoC Design Conference, 2016

Crosslink insertion for minimizing OCV clock skew.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Placement optimization for MP-DSAL compliant layout.
Proceedings of the International Conference on IC Design and Technology, 2016

Register grouping for synthesis of clock gating logic.
Proceedings of the International Conference on IC Design and Technology, 2016

OWARU: free space-aware timing-driven incremental placement.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Redundant via insertion in directed self-assembly lithography.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Redundant via insertion for multiple-patterning directed-self-assembly lithography.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Localized DNA circuit design with majority gates.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Buffer insertion to remove hold violations at multiple process corners.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Machine learning (ML)-based lithography optimizations.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Prosocial Activists in SNS: The Impact of Isomorphism and Social Presence on Prosocial Behaviors.
Int. J. Hum. Comput. Interact., 2015

Message from the technical program chairs.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Physical design and mask optimization for directed self-assembly lithography (DSAL).
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Physical synthesis of DNA circuits with spatially localized gates.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Identifying redundant inter-cell margins and its application to reducing routing congestion.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Simplifying Clock Gating Logic by Matching Factored Forms.
IEEE Trans. Very Large Scale Integr. Syst., 2014

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design and Optimization of Multiple-Mesh Clock Network.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Lithographic defect aware placement using compact standard Cells without inter-cell margin.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits.
J. Circuits Syst. Comput., 2013

A pipeline architecture with 1-cycle timing error correction for low voltage operations.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Analysis and minimization of short-circuit current in mesh clock network.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Pulsed-latch ASIC synthesis in industrial design flow.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Synthesis of Active-Mode Power-Gating Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Clock Gating Synthesis of Pulsed-Latch Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Synthesis of clock gating logic through factored form matching.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Gate delay modeling for static timing analysis of body-biased circuits.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Introducing irregularity to routing architecture of structured ASIC for better routability.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Retiming Pulsed-Latch Circuits With Regulating Pulse Width.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Pulsed-Latch Aware Placement for Timing-Integrity Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks.
J. Circuits Syst. Comput., 2011

Pulsed-Latch Circuits: A New Dimension in ASIC Design.
IEEE Des. Test Comput., 2011

Compact thermal models: Assessment and pitfalls.
Proceedings of the International SoC Design Conference, 2011

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Thermal signature: a simple yet accurate thermal index for floorplan optimization.
Proceedings of the 48th Design Automation Conference, 2011

Pulser gating: A clock gating of pulsed-latch circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Selectively patterned masks: Structured ASIC with asymptotically ASIC performance.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs.
ACM Trans. Design Autom. Electr. Syst., 2010

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Lookup Table-Based Adaptive Body biasing of Multiple Macros for Process Variation Compensation and Low Leakage.
J. Circuits Syst. Comput., 2010

Wakeup synthesis and its buffered tree construction for power gating circuit designs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Synthesis and implementation of active mode power gating circuits.
Proceedings of the 47th Design Automation Conference, 2010

Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Statistical time borrowing for pulsed-latch circuit designs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Minimizing leakage power of sequential circuits through mixed-<i>V<sub>t</sub></i> flip-flops and multi-<i>V<sub>t</sub></i> combinational gates.
ACM Trans. Design Autom. Electr. Syst., 2009

Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Frequency and yield optimization using power gates in power-constrained designs.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

HLS-l: High-level synthesis of high performance latch-based circuits.
Proceedings of the Design, Automation and Test in Europe, 2009

Register allocation for high-level synthesis using dual supply voltages.
Proceedings of the 46th Design Automation Conference, 2009

2008
Skewed Flip-Flop and Mixed-V<sub>t</sub> Gates for Minimizing Leakage in Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Power-gating-aware high-level synthesis.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

3-D thermal simulation with dynamic power profiles.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.
Proceedings of the 45th Design Automation Conference, 2008

Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Cell-Based Semicustom Design of Zigzag Power Gating Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Lookup Table-Based Adaptive Body Biasing of Multiple Macros.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Minimizing leakage power in sequential circuits by using mixed <i>V<sub>t</sub></i> flip-flops.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Power Analysis of VLSI Interconnect with RLC Tree Models and Model Reduction.
J. Circuits Syst. Comput., 2006

Physical design methodology of power gating circuits for standard-cell-based design.
Proceedings of the 43rd Design Automation Conference, 2006

Analysis and optimization of gate leakage current of power gating circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications.
IEEE Trans. Multim., 2005

A Mask Reuse Methodology for Reducing System-on-a-Chip Cost.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Analysis of power consumption in VLSI global interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power-aware slack distribution for hierarchical VLSI design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Architecting voltage islands in core-based system-on-a-chip designs.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
SEAS: a system for early analysis of SoCs.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Power distribution analysis of VLSI interconnects using model orderreduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Early analysis tools for system-on-a-chip design.
IBM J. Res. Dev., 2002

2001
Power-conscious Scheduling for Real-time Embedded Systems Design.
VLSI Design, 2001

Narrow bus encoding for low-power DSP systems.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Partial bus-invert coding for power optimization of application-specific systems.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Estimation of power distribution in VLSI interconnects.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Coupling-Driven Bus Design for Low-Power Application-Specific Systems.
Proceedings of the 38th Design Automation Conference, 2001

Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Schedulability-driven performance analysis of multiple mode embedded real-time systems.
Proceedings of the 37th Conference on Design Automation, 2000

Narrow bus encoding for low power systems.
Proceedings of ASP-DAC 2000, 2000

1999
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems.
Proceedings of the 36th Conference on Design Automation, 1999

1998
An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping.
Des. Autom. Embed. Syst., 1998

Partial bus-invert coding for power optimization of system level bus.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Rate Assignment for Embedded Reactive Real-Time Systems.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
An integrated hardware-software cosimulation environment with automated interface generation.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Software synthesis through task decomposition by dependency analysis.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Thread-based software synthesis for embedded system design.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995


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