Daiki Oki

According to our database, Daiki Oki authored at least 3 papers between 2011 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the Symposium on VLSI Circuits, 2012

2011

Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements.

Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the International SoC Design Conference, 2011