Daiki Hirabayashi

According to our database1, Daiki Hirabayashi authored at least 7 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A CMOS PWM Transceiver Using Self-Referenced Edge Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2013
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity.
J. Electron. Test., 2013

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the Symposium on VLSI Circuits, 2012

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Multi-bit sigma-delta TDC architecture with self-calibration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements.
Proceedings of the International SoC Design Conference, 2011


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