Naohiro Harigai

According to our database1, Naohiro Harigai authored at least 10 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
A CMOS PWM Transceiver Using Self-Referenced Edge Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
A low-offset cascaded time amplifier with reconfigurable inter-stage connection.
IEICE Electron. Express, 2014

2013
A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines.
IEICE Trans. Electron., 2013

Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption.
IEICE Electron. Express, 2013

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation.
IEEE J. Solid State Circuits, 2012

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the Symposium on VLSI Circuits, 2012

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements.
Proceedings of the International SoC Design Conference, 2011

An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011


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