Takahiro J. Yamaguchi

According to our database, Takahiro J. Yamaguchi authored at least 73 papers between 1997 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing.

Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2020

A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters.

Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka

IEEE Trans. Circuits Syst., 2020

Theoretical Analysis of Noise Figure for Modulated Wideband Converter.

Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing.

Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

IEICE Electron. Express, 2019

2018

A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture.

Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2016

A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators.

James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Experimental demonstration of stochastic comparators for fine resolution ADC without calibration.

Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

A CMOS PWM Transceiver Using Self-Referenced Edge Detection.

Kiichi Niitsu, Yusuke Osawa, Naohiro Harigai, Daiki Hirabayashi, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

IEEE Trans. Very Large Scale Integr. Syst., 2015

A new method for measuring alias-free aperture jitter in an ADC output.

Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma

Proceedings of the 2015 IEEE International Test Conference, 2015

Session 3 - Optical interconnect and reliability enhancement techniques.

Tetsuya Iizuka, Takahiro J. Yamaguchi

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters.

Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A low-offset cascaded time amplifier with reconfigurable inter-stage connection.

Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi

IEICE Electron. Express, 2014

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test.

Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri S. Fiez, Mike Peng Li

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer.

James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge.

Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines.

Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi

IEICE Trans. Electron., 2013

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity.

Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai

J. Electron. Test., 2013

Special session 12B: Panel post-silicon validation & test in huge variance era.

Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

A novel test structure for measuring the threshold voltage variance in MOSFETs.

Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 2013 IEEE International Test Conference, 2013

A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset.

James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Electrical and photonic I/O test and debug.

Mike Peng Li, Takahiro J. Yamaguchi

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation.

Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi

IEEE J. Solid State Circuits, 2012

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the Symposium on VLSI Circuits, 2012

A New Procedure for Measuring High-Accuracy Probability Density Functions.

Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Session Summary IV: Post-Silicon Measurements and Tests: Analog Test and High-Speed I/O Test II.

Takahiro J. Yamaguchi

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Post-Silicon Jitter Measurements.

Kiichi Niitsu, Takahiro J. Yamaguchi, Masahiro Ishida, Haruo Kobayashi

Proceedings of the 21st IEEE Asian Test Symposium, 2012

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.

Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Multi-bit sigma-delta TDC architecture with self-calibration.

Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Design for Testability That Reduces Linearity Testing Time of SAR ADCs.

Tomohiko Ogawa, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Satoshi Ito, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu

IEICE Trans. Electron., 2011

Application of a continuous-time level crossing quantization method for timing noise measurements.

Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu

Proceedings of the 2011 IEEE International Test Conference, 2011

Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements.

Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the International SoC Design Conference, 2011

An equivalent-time and clocked approach for continuous-time quantization.

Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology.

Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation.

Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

ADC linearity test signal generation algorithm.

Satoshi Uemori, Takahiro J. Yamaguchi, Satoshi Ito, Yohei Tan, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu, Nobuyoshi Ishikawa

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

SAR ADC that is configurable to optimize yield.

Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori, Nobukazu Takai, Kiichi Niitsu, Takahiro J. Yamaguchi, Tatsuji Matsuura, Nobuyoshi Ishikawa

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Stochastic TDC architecture with self-calibration.

Satoshi Ito, Shigeyuki Nishimura, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

A robust method for identifying a deterministic jitter model in a total jitter distribution.

Takahiro J. Yamaguchi, Kiyotaka Ichiyama, X. H. Hou, Masahiro Ishida

Proceedings of the 2009 IEEE International Test Conference, 2009

Phase-based alignment of two signals having partially overlapped spectra.

Albert Tumewu, Kazuyuki Miyazawa, Takafumi Aoki, Takahiro J. Yamaguchi, Katsuhiko Degawa, Takayuki Akita

Proceedings of the IEEE International Conference on Acoustics, 2009

2008

A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing.

Takahiro J. Yamaguchi, Masayuki Kawabata, Mani Soma, Masahiro Ishida, K. Sawami, Koichiro Uekusa

Proceedings of the 2008 IEEE International Test Conference, 2008

Total Jitter Measurement for Testing HSIO Integrated SoCs.

Takahiro J. Yamaguchi, Masahiro Ishida

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time.

Takahiro J. Yamaguchi, H. X. Hou, Koji Takayama, Dave Armstrong, Masahiro Ishida, Mani Soma

Proceedings of the 2007 IEEE International Test Conference, 2007

Data jitter measurement using a delta-time-to-voltage converter method.

Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma

Proceedings of the 2007 IEEE International Test Conference, 2007

An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter.

Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter.

Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Top 5 Issues in Practical Testing of High-Speed Interface Devices.

Takahiro J. Yamaguchi

Proceedings of the 16th Asian Test Symposium, 2007

2006

A Study of Per-Pin Timing Jitter Scope.

Takahiro J. Yamaguchi, Satoshi Iwamoto, Masahiro Ishida, Mani Soma

Proceedings of the 2006 IEEE International Test Conference, 2006

A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement.

Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

A wideband low-noise ATE-based method for measuring jitter in GHz signals.

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Skew measurements in clock distribution circuits using an analytic signal method.

Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems.

Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Loopback or not?

Takahiro J. Yamaguchi

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A Dynamically-Reconfigurable Image Recognition Processor.

Kazuyuki Maruo, Masayoshi Ichikawa, Naoto Miyamoto, Leo Karnan, Takahiro J. Yamaguchi, Koji Kotani, Tadahiro Ohmi

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003

Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method.

Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Toshifumi Watanabe, Tadahiro Ohmi

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division.

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha

J. Electron. Test., 2003

Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements.

Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Open Architecture ATE and 250 Consecutive UIs.

Takahiro J. Yamaguchi

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

A Method for Compressing Test Data Based on Burrows-Wheeler Transformation.

Takahiro J. Yamaguchi, Dong Sam Ha, Masahiro Ishida, Tadahiro Ohmi

IEEE Trans. Computers, 2002

Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division.

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter.

Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Multi-GHz interface devices should be tested using external test resources.

Takahiro J. Yamaguchi

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices.

Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals.

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Testing clock distribution circuits using an analytic signal method.

Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

A new approach to built-in self-testable datapath synthesis based on integer linear programming.

Han Bin Kim, Dong Sam Ha, Takeshi Takahashi, Takahiro J. Yamaguchi

IEEE Trans. Very Large Scale Integr. Syst., 2000

Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method.

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Toshifumi Watanabe, Tadahiro Ohmi

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Jitter measurements of a PowerPC^TM microprocessor using an analytic signal method.

Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1998

COMPACT: A Hybrid Method for Compressing Test Data.

Masahiro Ishida, Dong Sam Ha, Takahiro J. Yamaguchi

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Dynamic Testing of ADCs Using Wavelet Transforms.

Takahiro J. Yamaguchi, Mani Soma

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

An Efficient Method for Compressing Test Data.

Takahiro J. Yamaguchi, Masahiro Ishida, Marco Tilgner, Dong Sam Ha

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Static Testing of ADCs Using Wavelet Transforms.

Takahiro J. Yamaguchi

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997