Damiano Fagotti

According to our database, Damiano Fagotti authored at least 4 papers in 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A -66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC.

Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving -62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise.

Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni Rocco Trotta, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A DTC-Based Digital PLL Achieving -64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDC.

Riccardo Moleri, Daniele Lodi Rizzini, Michele Rossoni, Damiano Fagotti, Pietro Salvi, Stefano Gallucci, Andrea Leonardo Lacaita, Salvatore Levantino, Simone Mattia Dartizio

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mVpp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance Tuning.

Stefano Gallucci, Daniele Lodi Rizzini, Riccardo Moleri, Michele Rossoni, Pietro Salvi, Damiano Fagotti, Francesco Tesolin, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026